ADC Capabilities Teensy 3.5 and 3.6

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gsi11135

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Thank you for the TEENSY!

What are the sample rates attainable on a single ADC line? Multiple ADC lines? Simultaneous sampling rates for both ADCs being utilized?

Joseph
 
The maximum ADC clock speed for Teensy 3.5 is a bit faster than for the rest, 24 vs. 18 MHz (not for 16 bits precision, for which it's 12 MHz for all boards).
In the ADC library, this means that the sample rates are the same except for T3.5 at the highest speed settings for some F_BUS settings. (see ADC_Module.h for more info.)
 
Basically, it comes down to a number of factors that you have to consider.

The maximum clock speed for the ADC is one issue.
Another is the desired resolution - the higher the desired resolution, the slower the sampling has to be.
Input impedance - you may need a good analog front end / buffer to present a clean signal to the ADC
Noise in the signal - you may need to average samples to reduce impact of spikes.
Any processing you're doing to the signal between samples.
Etc.

All these factors influence sampling speed. Thus, a blanket statement is not possible. We would need to know more about what you are trying to sample and what computations the Teensy is performing between samples. I've had simple programs run analog and digital samples on multiple channels at 11kHz+ and faster speeds are likely possible (see Bill Greimans efforts with the SDFAT library and the fast analog logger example in there). Pedevide also provides good examples in his Teensy ADC library.

If the application is demanding (i.e. 12+ ENOB, 20+kHz sampling rate, bipolar signal, etc.) then using a dedicated external ADC via SPI might be a better idea.
 
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I want to use teensy 3.6 for signal processing two analog signals (beat frequency and sync signal) from a FMCW radar, I wonder the teeny 3.6 will be capable to digitalize both signlas at the same time with a sample rate greater than 44 kHz and 16 bits, then stores them in a sd card. Actually, the analog frond end improves gain and filters at 15 kHz to the ADC. Can I do this using the ADC teensy? Could I use teensy to store this data?. Any hints will be great. Thanks!
 
Something seems off with the Teensy A/D Input Impedance

When connecting the output from a precision voltage divider both 5k/5k and 20k/20k (0.005% tolerance) to the Teensy Analog Input, a 4.096V precision reference is being divided down to half (2.048V) and hopefully read on the Teensy 3.5 A/D single pin or differential input. However, when the Teensy A/D pin A2 is connected to the middle of the voltage divider, the voltage INCREASES from 2.048V without Teensy attached to 2.158V when the Teensy analog input pin A2 is connected, as measured from the middle of the divider to ground wtih good quality DMM.

This should be impossible, as the voltage divider resistance cannot increase when adding additional high impedance inputs. If I test the Teensy Analog input when floating (not attached to anything) it floats at 3.0V. I'm guessing there is an internal pull-up resistor somehow enabled or the 3.0V on the A/D input is raising the 2.0148V at the voltage divider to 2.158V after Teensy is connected.

Without using an OPamp or Buffer, is there an explanation why the resistance or voltage is increasing and how to correct this in the sketch to properly utilize a precision voltage divider?

Thanks
 
Jerry said:
Something seems off with the Teensy A/D Input Impedance
Click to expand...

Maybe you're using pinMode(pin, INPUT) which turns on the digital circuitry, or even pinMode(pin, INPUT_PULLUP), when you should just leave it alone or use pinMode(pin, INPUT_DISABLE).

Really, just a blind guess without being able to see your code....
 
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