Basically, it comes down to a number of factors that you have to consider.
The maximum clock speed for the ADC is one issue.
Another is the desired resolution - the higher the desired resolution, the slower the sampling has to be.
Input impedance - you may need a good analog front end / buffer to present a clean signal to the ADC
Noise in the signal - you may need to average samples to reduce impact of spikes.
Any processing you're doing to the signal between samples.
Etc.
All these factors influence sampling speed. Thus, a blanket statement is not possible. We would need to know more about what you are trying to sample and what computations the Teensy is performing between samples. I've had simple programs run analog and digital samples on multiple channels at 11kHz+ and faster speeds are likely possible (see Bill Greimans efforts with the SDFAT library and the fast analog logger example in there). Pedevide also provides good examples in his Teensy ADC library.
If the application is demanding (i.e. 12+ ENOB, 20+kHz sampling rate, bipolar signal, etc.) then using a dedicated external ADC via SPI might be a better idea.