ISRbottom, usb_task_state: 0x3
PCI Vbus state changed to 2
USB host speed now 2
ISRbottom, usb_task_state: 0x3
ISRbottom, usb_task_state: 0x5
ISRbottom, usb_task_state: 0xC
ISRbottom, UHS_USB_HOST_STATE_CONFIGURING
Configuring: parent = 0, port = 1, speed = 2
Configuring PktSize 0x40, rcode: 0x00, retries 0,
ctrlReqOpen
SetAddress, addr=0, ep=0
ep entry for interface 0 ep 0 max packet size = 64
SetAddress, speed=2, maxlen=64
SetAddress, parent=0, parent_port=1
ctrlReq2: left: 64, read:64, nbytes 64
ctrlReqRead left: 64, nbytes: 64, dataptr: 2002fe78
InTransfer 64
ctrlReq3: acceptBuffer sz 18 nbytes 64 left 46
PCI Vbus state changed to 2
USB host speed now 2
ctrlReqOpen
SetAddress, addr=0, ep=0
ep entry for interface 0 ep 0 max packet size = 64
SetAddress, speed=2, maxlen=64
SetAddress, parent=0, parent_port=1
0 retries.
DevDescr 2nd poll, bMaxPacketSize0:64
ctrlReqOpen
SetAddress, addr=1, ep=0
ep entry for interface 0 ep 0 max packet size = 64
SetAddress, speed=2, maxlen=64
SetAddress, parent=0, parent_port=1
ctrlReq2: left: 18, read:18, nbytes 18
ctrlReqRead left: 18, nbytes: 18, dataptr: 2002fe78
InTransfer 18
PCI Vbus state changed to 2
USB host speed now 2
ctrlReqOpen
SetAddress, addr=0, ep=0
ep entry for interface 0 ep 0 max packet size = 64
SetAddress, speed=2, maxlen=64
SetAddress, parent=0, parent_port=1
0 retries.
configs: 1