Still have Timer questions about the 3.6 Teensy

Status
Not open for further replies.
C

ceremona

Well-known member
Hi Folks,

I understand, from various postings and conversations, that Teensy 3.6 has 4 independent timer "blocks" that would allow for one to use 4 different values for analogWriteFrequency (as stated in the PWM section https://www.pjrc.com/teensy/td_pulse.html) , but it still doesn't clarify how many total IntervalTimer calls are allowed in software for the 3.6. As a comparison, the 3.2 Teensy is documented to have 3 Timer blocks and is limited to a total of 4 IntervalTimer calls.

Could someone clarify?

Also, since the 3.6/3.5 Teensy is one sale on the pjrc website it might be good to centrally publish the pinout information sheet on the website rather than requiring people to dig through these painful forums for the information. Just a thought. I know we're all busy here.
 
PWM / analogWrite is using the FTM timers. The FTM modules (4 on Teensy 3.6, 3 on T3.1/3.2, 2 on T3.0) use 16-bit counters and can be used as timers (can trigger interrupts). TimerOne / TimerThree are based on FTM timers.

IntervalTimer is using PIT timers - a completely different timer module, which coincidentally supports 4 counters / timers with 32-bit counters.
 
ceremona said:
but it still doesn't clarify how many total IntervalTimer calls are allowed in software for the 3.6.
Click to expand...

The answer is 4.

IntervalTimer uses the PIT timers, which are separate from the FTM timers used for analogWrite / PWM.

Teensy 3.0, 3.1, 3.2, 3.5 and 3.6 have 4 PIT timers.

Teensy LC has 2 PIT timers.
 
The complete pinout information is discover-able. The problem is there is a ton of information one could publish on the pinout cards, unfortunately putting too much data on the card would probably make it very confusing for the majority of users. But simply having the mapping for which Teensy pin maps to which processor pin and access to the datasheet you can extract the data. Yes, there are times I wish there was more data available on the card, like not only that some pin is a CS pin for SPI1, but which channel. The majority of people may not care, but if you have something like the ILI9341 display which takes 2, then you need to make sure they are on unique channels. But I understand adding more here on default card may confuse more people so I understand why Paul chooses to minimize some of this and instead have the card concentrate on what will hopefully help the most people.

Hopefully soon, now that the Beta is done, PJRC will migrate to the new board software and enable a Wiki, which will hopefully allow more data to be summarized at a convenient location.

One of the first things I (and several others) did when I received the Beta board, was to do that mapping and get the information from the reference manual. I put all of that into my own spreadsheet which I have uploaded a few times. Others have done so as well. Which looks like:
Code: 
	Pin Name	Default	ALT0	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7
0	PTB16	TSI0_CH9	TSI0_CH9	PTB16	SPI1_SOUT	UART0_RX	FTM_CLKIN0	FB_AD17/SDRAM_D17	EWM_IN	TPM_CLKIN0
1	PTB17	TSI0_CH10	TSI0_CH10	PTB17	SPI1_SIN	UART0_TX	FTM_CLKIN1	FB_AD16/SDRAM_D16	EWM_OUT_b	TPM_CLKIN1
2	PTD0/LLWU_P12	DISABLED		PTD0/LLWU_P12	SPI0_PCS0	UART2_RTS_b	FTM3_CH0	FB_ALE/FB_CS1_b/FB_TS_b		
3	PTA12	CMP2_IN0	CMP2_IN0	PTA12	CAN0_TX	FTM1_CH0	RMII0_RXD1/MII0_RXD1	I2C2_SCL	I2S0_TXD0	FTM1_QD_PHA/TPM1_CH0
4	PTA13/LLWU_P4	CMP2_IN1	CMP2_IN1	PTA13/LLWU_P4	CAN0_RX	FTM1_CH1	RMII0_RXD0/MII0_RXD0	I2C2_SDA	I2S0_TX_FS	FTM1_QD_PHB/TPM1_CH1
5	PTD7	DISABLED		PTD7	CMT_IRO	UART0_TX	FTM0_CH7	SDRAM_CKE	FTM0_FLT1	SPI1_SIN
6	PTD4/LLWU_P14	DISABLED		PTD4/LLWU_P14	SPI0_PCS1	UART0_RTS_b	FTM0_CH4	FB_AD2/SDRAM_A10	EWM_IN	SPI1_PCS0
7	PTD2/LLWU_P13	DISABLED		PTD2/LLWU_P13	SPI0_SOUT	UART2_RX	FTM3_CH2	FB_AD4/SDRAM_A12		I2C0_SCL
8	PTD3	DISABLED		PTD3	SPI0_SIN	UART2_TX	FTM3_CH3	FB_AD3/SDRAM_A11		I2C0_SDA
9	PTC3/LLWU_P7	CMP1_IN1	CMP1_IN1	PTC3/LLWU_P7	SPI0_PCS1	UART1_RX	FTM0_CH2	CLKOUT	I2S0_TX_BCLK	
10	PTC4/LLWU_P8	DISABLED		PTC4/LLWU_P8	SPI0_PCS0	UART1_TX	FTM0_CH3	FB_AD11/SDRAM_A19	CMP1_OUT	
11	PTC6/LLWU_P10	CMP0_IN0	CMP0_IN0	PTC6/LLWU_P10	SPI0_SOUT	PDB0_EXTRG	I2S0_RX_BCLK	FB_AD9/SDRAM_A17	I2S0_MCLK	
12	PTC7	CMP0_IN1	CMP0_IN1	PTC7	SPI0_SIN	USB0_SOF_OUT	I2S0_RX_FS	FB_AD8/SDRAM_A16		
13	PTC5/LLWU_P9	DISABLED		PTC5/LLWU_P9	SPI0_SCK	LPTMR0_ALT2	I2S0_RXD0	FB_AD10/SDRAM_A18	CMP0_OUT	FTM0_CH2
14	PTD1	ADC0_SE5b	ADC0_SE5b	PTD1	SPI0_SCK	UART2_CTS_b	FTM3_CH1	FB_CS0_b		
15	PTC0	ADC0_SE14/TSI0_CH13	ADC0_SE14/TSI0_CH13	PTC0	SPI0_PCS4	PDB0_EXTRG	USB0_SOF_OUT	FB_AD14/SDRAM_A22	I2S0_TXD1	
16	PTB0/LLWU_P5	ADC0_SE8/ADC1_SE8/TSI0_CH0	ADC0_SE8/ADC1_SE8/TSI0_CH0	PTB0/LLWU_P5	I2C0_SCL	FTM1_CH0	RMII0_MDIO/MII0_MDIO	SDRAM_CAS_b	FTM1_QD_PHA/TPM1_CH0	
17	PTB1	ADC0_SE9/ADC1_SE9/TSI0_CH6	ADC0_SE9/ADC1_SE9/TSI0_CH6	PTB1	I2C0_SDA	FTM1_CH1	RMII0_MDC/MII0_MDC	SDRAM_RAS_b	FTM1_QD_PHB/TPM1_CH1	
18	PTB3	ADC0_SE13/TSI0_CH8	ADC0_SE13/TSI0_CH8	PTB3	I2C0_SDA	UART0_CTS_b/UART0_COL_b	ENET0_1588_TMR1	SDRAM_CS0_b	FTM0_FLT0	
19	PTB2	ADC0_SE12/TSI0_CH7	ADC0_SE12/TSI0_CH7	PTB2	I2C0_SCL	UART0_RTS_b	ENET0_1588_TMR0	SDRAM_WE	FTM0_FLT3	
20	PTD5	ADC0_SE6b	ADC0_SE6b	PTD5		UART0_CTS_b/UART0_COL_b	FTM0_CH5	FB_AD1/SDRAM_A9	EWM_OUT_b	SPI1_SCK
21	PTD6/LLWU_P15	ADC0_SE7b	ADC0_SE7b	PTD6/LLWU_P15	SPI0_PCS3	UART0_RX	FTM0_CH6	FB_AD0	FTM0_FLT0	SPI1_SOUT
22	PTC1/LLWU_P6	ADC0_SE15/TSI0_CH14	ADC0_SE15/TSI0_CH14	PTC1/LLWU_P6	SPI0_PCS3	UART1_RTS_b	FTM0_CH0	FB_AD13/SDRAM_A21	I2S0_TXD0	
23	PTC2	ADC0_SE4b/CMP1_IN0/TSI0_CH15	ADC0_SE4b/CMP1_IN0/TSI0_CH15	PTC2	SPI0_PCS2	UART1_CTS_b	FTM0_CH1	FB_AD12/SDRAM_A20	I2S0_TX_FS	
24	PTE26	DISABLED		PTE26	ENET_1588_CLKIN	UART4_CTS_b			RTC_CLKOUT	USB0_CLKIN
25	PTA5	DISABLED		PTA5	USB0_CLKIN	FTM0_CH2	RMII0_RXER/MII0_RXER	CMP2_OUT	I2S0_TX_BCLK	JTAG_TRST_b
26	PTA14	DISABLED		PTA14	SPI0_PCS0	UART0_TX	RMII0_CRS_DV/MII0_RXDV	I2C2_SCL	I2S0_RX_BCLK	I2S0_TXD1
27	PTA15	CMP3_IN1	CMP3_IN1	PTA15	SPI0_SCK	UART0_RX	RMII0_TXEN/MII0_TXEN		I2S0_RXD0	
28	PTA16	CMP3_IN2	CMP3_IN2	PTA16	SPI0_SOUT	UART0_CTS_b/UART0_COL_b	RMII0_TXD0/MII0_TXD0		I2S0_RX_FS	I2S0_RXD1
29	PTB18	TSI0_CH11	TSI0_CH11	PTB18	CAN0_TX	FTM2_CH0	I2S0_TX_BCLK	FB_AD15/SDRAM_A23	FTM2_QD_PHA/TPM2_CH0	
30	PTB19	TSI0-CH12	TSI0_CH12	PTB19	CANO_RX	FTM2_CH1	I2S0_TX_FS	FB_OE_b	FTM2_QD_PHB/TPM2_CH1	
31	PTB10	ADC1_SE14	ADC1_SE14	PTB10	SPI1_PCS0	UART3_RX		FB_AD19/SDRAM_D19	FTM0_FLT1	
32	PTB11	ADC1_SE15	ADC1_SE15	PTB11	SPI1_SCK	UART3_TX		FB_AD18/SDRAM_D18	FTM0_FLT2	
33	PTE24	ADC0_SE17	ADC0_SE17	PTE24	CAN1_TX	UART4_TX		I2C0_SCL	EWM_OUT_b	
34	PTE25/LLWU_P21	ADC0_SE18	ADC0_SE18	PTE25/LLWU_P21	CAN1_RX	UART4_RX		I2C0_SDA	EWM_IN	
35	PTC8	ADC1_SE4b/CMP0_IN2	ADC1_SE4b/CMP0_IN2	PTC8		FTM3_CH4	I2S0_MCLK	FB_AD7/SDRAM_A15		
36	PTC9	ADC1_SE5b/CMP0_IN3	ADC1_SE5b/CMP0_IN3	PTC9		FTM3_CH5	I2S0_RX_BCLK	FB_AD6/SDRAM_A14	FTM2_FLT0	
37	PTC10	ADC1_SE6b	ADC1_SE6b	PTC10	I2C1_SCL	FTM3_CH6	I2S0_RX_FS	FB_AD5/SDRAM_A13		
38	PTC11/LLWU_P11	ADC1_SE7b	ADC1_SE7b	PTC11/LLWU_P11	I2C1_SDA	FTM3_CH7	I2S0_RXD1	FB_RW_b		
39	PTA17	ADC1_SE17	ADC1_SE17	PTA17	SPI0_SIN	UART0_RTS_b	RMII0_TXD1/MII0_TXD1		I2S0_MCLK	
										
Updates in Core Pins.h										
40	A28	DISABLED		PTA28			MII0_TXER		FB_A25	
41	A29	DISABLED		PTA29			MII0_COL		FB_A24	
42	A26	DISABLED		PTA26			MII0_TXD3		FB_A27	
43	B20	DISABLED		PTB20	SPI2_PCS0			FB_AD31/SDRAM_D31	CMP0_OUT	
44	B22	DISABLED		PTB22	SPI2_SOUT			FB_AD29/SDRAM_D29	CMP2_OUT	
45	B23	DISABLED		PTB23	SPI2_SIN	SPI0_PCS5		FB_AD28/SDRAM_D28	CMP3_OUT	
46	B21	DISABLED		PTB21	SPI2_SCK			FB_AD30/SDRAM_D30	CMP1_OUT	
47	D8	DISABLED		PTD8/LLWU_P24	I2C0_SCL			LPUART0_RX	FB_A16	
48	D9	DISABLED		PTD9	I2C0_SDA			LPUART0_TX	FB_A17	
49	B4	ADC1_SE10	ADC1_SE10	PTB4			ENET0_1588_TMR2	SDRAM_CS1-b	FTM1_FLT0	
50	B5	ADC1_SE11	ADC1_SE11	PTB5			ENET0_1588_TMR3		FTM2_FLT0	
51	D14	DISABLED		PTD14	SPI2_SIN		SDHC0_D6		FB_A22	
52	D13	DISABLED		PTD13	SPI2_SOUT		SDHC0_D5		FB_A21	
53	D12	DISABLED		PTD12	SPI2_SCK	FTM3_FLT0	SDHC0_D4		FB_A20	
54	D15	DISABLED		PTD15	SPI2_PCS1		SDHC0_D7	FB_A23		
55	D11	DISABLED		PTD11/LLWU_P25	SPI2_PCS0		SDHC0_CLKIN	LPUART0_CTS_b	FB_A19	
56	E10	DISABLED		PTE10/LLWU_P18	I2C3_SDA		I2S0_TXD0	LPUART0_CTS_b	FTM3_CH5	USB1_ID
57	E11	DISABLED		PTE11	I2C3_SCL		I2S0_TX_FS	LPUART0_RTS_b	FTM3_CH6	
										
A10	ADC1_DP0/ADC0_DP3		ADC1_DP0/ADC0_DP3							
A11	ADC1_DM0/ADC0_DM3		ADC1_DM0/ADC0_DM3							
Aref										
										
5 PIN USB HOST										
G										
G										
D+	J1									
D-	K1									
5V										
										
										
On-board SD card (dedicated 4-bit SDIO)										
----------------										
58	PTE0	ADC1_SE4a	ADC1_SE4a	PTE0	SPI1_PCS1	UART1_TX	SDHC1_D1	TRACE_CLKOUT	I2C1_SDA	RTC_CLKOUT
59	PTE1	ADC1_SE5a	ADC1_SE5a	PTE1/LLWU_P0	SPI1_SOUT	UART1_RX	SDHC0_D0	TRACE_D3	I2C1_SCL	SPI1_SIN
60	PTE2	PTE2/LLWU_P1	ADC1_SE6a	PTE2/LLWU_P1	SPI1_SCK	UART1_CTS_b	SDHC0_DCLK	TRACE_D2		
61	PTE3	ADC1_SE7a	ADC1_SE7a	PTE3	SPI1_SIN	UART1_RTS_b	SDHC0_CMD	TRACE_D1		SPI1_SOUT
62	PTE4	DISABLED		PTE4/LLWU_P2	SPI1_PCS0	UART3_TX	SDHC0_D3	TRACE_D0		
63	PTE5	DISABLED		PTE5	SPI1_PCS2	UART3_RX	SDHC0_D2		FTM3_CH0
Sorry, I did not try to convert tabs and the like to get everything into their own columns, but it shows the raw data.
 
I was simply responding to the non-helpful comment that this information was available on the card, not whether the information is "discoverable".

Yes, I understand that it's impossible to fit all the complex information about timers on the card, and I have no issues with that. Very much looking forward to a more helpful wiki format when it comes to finding information on the pjrc site, however!
 
Status
Not open for further replies.
Back
Top