Advice for working with multiple audio I/Os

[DiamondDrake]

I've been reading though the audio library code for hours and it's difficult to digest, the datasheet for the micro is 2k pages, but I'm having a lot of fun playing with the teensy.

That said I need some advice. The primary source of audio INto my project will be a chip that is IS2 Master only, not a problem the audio library has a slave input. If slave input i2s is used, then slave output i2s has to be used, according to the GUI tool documentation.

So, is it acceptable to use the clocks from the the chip that is master to drive both the teensy and the audio chip that the teensy will be outputting audio to?

something like:

[Master audio I2S OUT CHIP] -----> teensy ------> SGTL5000(or similar)
L_______________clocks___________________________^


after reading gratuitous amounts of i2s and sai literature, I'm still not entirely sure in what way data is required to be synchronized.

if this shared clock system can work, If I needed to be able to optionally use a different audio input. What options do I have? Since the PWM and ADC say they "should not be used" in the docs when using slave.

would it work to just mux the datastream to pin 13 from the SGTL5000's output(ADC line in), still using the original Master Audio's clocks on 23 and 9?

could the MCLK for the sgtl5000 still be generated by the teensy?

I will eventually try and come to all the conclusions, but some experienced audio dev/user foresight could save me days of frustration and dead ends.

thank you for your time!

 

[WMXZ]

So, is it acceptable to use the clocks from the the chip that is master to drive both the teensy and the audio chip that the teensy will be outputting audio to?

Yes, you can connect multiple slaves to master, you should also connect L/R and bit clock to all slaves in parallel.
only data lines go to different devices
overall synchronization is done by Master I2S

You would then run RX and TX at the same time. You would follow the following double buffer processing scheme

receive into buffer1 and transmit from buffer2
process buffer1 into buffer2
receive into buffer2 and transmit from buffer1
process buffer2 into buffer1
receive into buffer1 and transmit from buffer2
etc.

 

[PaulStoffregen]

The I2S slave code is buggy. It's had pretty much no maintenance since the earliest days before switching to SGTL5000.

If you do try it, please report issues as best you can. Maybe it's finally time to fix up that very old code....

 

[DiamondDrake]

Yes, you can connect multiple slaves to master, you should also connect L/R and bit clock to all slaves in parallel.
only data lines go to different devices
overall synchronization is done by Master I2S

You would then run RX and TX at the same time. You would follow the following double buffer processing scheme

receive into buffer1 and transmit from buffer2
process buffer1 into buffer2
receive into buffer2 and transmit from buffer1
process buffer2 into buffer1
receive into buffer1 and transmit from buffer2
etc.

I'm not sure I follow the pipeline, but I think I see what you're getting at. I'm glad to know that it's possible.

The I2S slave code is buggy. It's had pretty much no maintenance since the earliest days before switching to SGTL5000.

If you do try it, please report issues as best you can. Maybe it's finally time to fix up that very old code....

I definitely will be trying it. I've already ordered all the chips and and I'm banking my senior design project at university on being able to get it to work. I'm sure I'll be posting back questions and issues as it goes along. Tuesday a small team of developers and I are getting together to beta test the pipeline. I'll report my findings.


Where do you suggest I start reading to fully understand the pipeline for the audio library? I understand it on a block diagram level, but its not clear how all the magic pipes work that get data into and out of "blocks"

 

[PaulStoffregen]

The audio lib connections are in AudioStream.cpp and AudioStream.h in the core lib.