DiamondDrake
Member
I've been reading though the audio library code for hours and it's difficult to digest, the datasheet for the micro is 2k pages, but I'm having a lot of fun playing with the teensy.
That said I need some advice. The primary source of audio INto my project will be a chip that is IS2 Master only, not a problem the audio library has a slave input. If slave input i2s is used, then slave output i2s has to be used, according to the GUI tool documentation.
So, is it acceptable to use the clocks from the the chip that is master to drive both the teensy and the audio chip that the teensy will be outputting audio to?
something like:
[Master audio I2S OUT CHIP] -----> teensy ------> SGTL5000(or similar)
L_______________clocks___________________________^
after reading gratuitous amounts of i2s and sai literature, I'm still not entirely sure in what way data is required to be synchronized.
if this shared clock system can work, If I needed to be able to optionally use a different audio input. What options do I have? Since the PWM and ADC say they "should not be used" in the docs when using slave.
would it work to just mux the datastream to pin 13 from the SGTL5000's output(ADC line in), still using the original Master Audio's clocks on 23 and 9?
could the MCLK for the sgtl5000 still be generated by the teensy?
I will eventually try and come to all the conclusions, but some experienced audio dev/user foresight could save me days of frustration and dead ends.
thank you for your time!
That said I need some advice. The primary source of audio INto my project will be a chip that is IS2 Master only, not a problem the audio library has a slave input. If slave input i2s is used, then slave output i2s has to be used, according to the GUI tool documentation.
So, is it acceptable to use the clocks from the the chip that is master to drive both the teensy and the audio chip that the teensy will be outputting audio to?
something like:
[Master audio I2S OUT CHIP] -----> teensy ------> SGTL5000(or similar)
L_______________clocks___________________________^
after reading gratuitous amounts of i2s and sai literature, I'm still not entirely sure in what way data is required to be synchronized.
if this shared clock system can work, If I needed to be able to optionally use a different audio input. What options do I have? Since the PWM and ADC say they "should not be used" in the docs when using slave.
would it work to just mux the datastream to pin 13 from the SGTL5000's output(ADC line in), still using the original Master Audio's clocks on 23 and 9?
could the MCLK for the sgtl5000 still be generated by the teensy?
I will eventually try and come to all the conclusions, but some experienced audio dev/user foresight could save me days of frustration and dead ends.
thank you for your time!