I2S custom speed

[WMXZ]

This post is for custom I2S applications (i.e. not Audio lib based)
I spent a week or so chasing some problems with my application, where the I2S-DMA combo ceased to function when float FFT was in use.

In the end it turned out, that the MCLK chosen to obtain bit clock, was with 96 MHz far too high. My ADC does not need a MCLK feed so I have chosen a convenient MCLK for my bit rate clock. After designing my bit-clock calculation around 48 Mhz the program runs (so far) without obvious I2S-DMA issues. 48 MHz is still about twice the "Up to 25 MHz" note in the K66 datasheet, so one may have to go a little bit slower, if further stability problem occur.

I question remain, why this instability is connected with float FFT. A guess is, that the FPU, which need more power than the integer CPU, generates too much heat for I2S MCLK PLL to function correctly.

 

[Frank B]

Too much heat ? That would heat the whole chip - is it warm ?? (i've never seen a warm teensy )

 

[WMXZ]

Too much heat ? That would heat the whole chip - is it warm ?? (i've never seen a warm teensy )

Yes, K66 is warm (not hot), I'm doing 5864 256-point arm_rfft_fast_f32 per second (I2S Quad: 4 FFTs on 256 samples every 0.68 ms, @240 MHz F_CPU)
(processing needs 0.58 ms of 0.68 ms available)

Also, different K66 did 'fail' at different times (one after minutes of operation, an other immediately) and locality of the FPU within the chip matters. (say if it is close to the I2S PLL, or not)

 

[Frank B]

Hard to believe, that temperature is the reason.
The teensy would never work with 85°C

I've noticed these I2S -problems, too - with overclocking to 216/240MHz F_CPU (T3.6)

 

[PaulStoffregen]

FWIW, I do have the I2S overclocking issue on my todo list, but not planning to look at it until after a stable 1.31 release.

 

[Frank B]

Maybe a lower MCLK works better ? I think, it may be worth a try...

 

[WMXZ]

Maybe a lower MCLK works better ? I think, it may be worth a try...

Yes, that is the key message, maybe not formulated clear enough.
even if my ADC does not require an explicit MCLK line, the bit clock is generated via the MCLK. It this intermediate MCLK is too high, I got stability issues. with a MCLK of 48 MHz I2S seem to work
two examples
to generate frame sync (or L/R) of 375 kHz with F_CPU 240 MHz and 16 bit words

can use MCLK 96 MHz, or

I2S0_MDR = I2S_MDR_FRACT(1) | I2S_MDR_DIVIDE(4);
I2S0_RCR2 |= I2S_RCR2_DIV(3)

which is not stable

or one could use a MCLK of 48 MHz

I2S0_MDR = I2S_MDR_FRACT(0) | I2S_MDR_DIVIDE(4);
I2S0_RCR2 |= I2S_RCR2_DIV(1)

which turned out to be stable

again datasheet says MCLK u to 25 MHz, but is seems 48 MHz is save overclocking