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Thread: Are SPI signals CS0 and CS1 meaningful?

  1. #1

    Are SPI signals CS0 and CS1 meaningful?

    I have a TeensyLC.

    On the picture card included with the board, the top surface picture shows CS0 and CS1 as pins as belonging to the SPI-0 and SPI-1 Serial Peripheral Buses.

    The SPI library only supports Master Mode.
    Slave Mode is not supported.
    So in Master Mode, I should be able to use any I/O pin as my Slave-Select...an not be tied to CS0 and CS1 in any way.

    In fact, I should be able to use CS0 and CS1 as I/O pins doing something entirely different.

    Isn't that correct?

  2. #2
    Senior Member+ MichaelMeissner's Avatar
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    Yes and no. Most SPI drivers can use any pin. Some drivers are optimized for using a particular CS pin. I believe in the LC, there is only one hardware CS pin for each of the two spi buses. The 3.2/3.5/3.6 have 5 hardware CS pins for the first SPI bus (9, 10, 15, 20, 21)

  3. #3
    Senior Member+ KurtE's Avatar
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    As Michael mentioned, most libraries and user code that does SPI, use standard GPIO pins to control the CS pin for their hardware. So in that case no it does not mater. As you mentioned the SPI library only does master mode and as such the SS pin is not used.

    On some of the other chips, like the 3.2, 3.5, 3.6, you have the ability to encode CS data as part of a command you queue up to the SPI hardware. This is used in a few libraries, such as the ili9341_t3, to enable the code to speed up. SPI0 on these devices have a queue of 4 entries and by allowing you to control the DC (Data/Command), line as part of the command, it allows you to queue up things like a command to set the X range, immediately followed by the 4 bytes of the range and the SPI code will automatically raise/lower the DC line while allowing the the SPI buss to be running at full speed. Without this, you typically have to wait for the queue to empty, logically turn on DC(digitalWrite), Queue up the command, wait until it completes, logically turn off DC, and queue up the data...

  4. #4
    Thanks guys...

    I'm not planning on using any fancy queuing FIFO's on SPI...just plain old single byte-by-byte sending/receiving.

    So I guess I can use any I/O pin as SS/CS(slave select/chip select)....and at the same time use hardware CS0 and CS1 as regular old IO pins..

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