Here's my attempt at porting OctoWS2811 to Teensy LC. It does seem work, based on my minimal testing. I've tested with a 6-pixel strip of WS2812B chips and a 22-pixel strand of WS2811 chips. In both cases, I drove the pixels directly from the Teensy's GPIO pins (no buffer chip available to change the logic level). I lowered the Vin voltage to the pixels to compensate. I also examined the GPIO output with a logic analyzer. The timing isn't perfectly consistent but it seems to be good enough for my tests. Perhaps it's not good enough in every situation, though.
The most significant things I changed from Paul's code.
1) Added a new formula for the timer mod: F_CPU / frequency - 1 (consistent with the datasheet).
2) Changed the trigger order, so CH0 triggers DMA1, CH1 triggers DMA2 and OV triggers DMA3. (Original order had OV triggering DMA1, but I found OV is the last event.)
3) I found that DMA3 doesn't always set the output low at the end of the stream. It does always seem to generate the interrupt. I haven't figured out why this happens, but I added a workaround by setting the output low in the ISR.
So really I just tweaked the code that Paul had already added.
Not sure if this is good enough to upstream into the official library, but maybe someone will find it useful.
Cheers!
The most significant things I changed from Paul's code.
1) Added a new formula for the timer mod: F_CPU / frequency - 1 (consistent with the datasheet).
2) Changed the trigger order, so CH0 triggers DMA1, CH1 triggers DMA2 and OV triggers DMA3. (Original order had OV triggering DMA1, but I found OV is the last event.)
3) I found that DMA3 doesn't always set the output low at the end of the stream. It does always seem to generate the interrupt. I haven't figured out why this happens, but I added a workaround by setting the output low in the ISR.
So really I just tweaked the code that Paul had already added.
Not sure if this is good enough to upstream into the official library, but maybe someone will find it useful.
Cheers!