In KinetisSDHC.c there is a macro used to set the SDHC clock speed:
Code:
// prescale can be 2, 4, 8, 16, 32, 64, 128, 256
// divisor can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
#define SDHC_SYSCTL_DIVISOR(prescale, divisor) \
(SDHC_SYSCTL_DVS((prescale)>>1)|SDHC_SYSCTL_SDCLKFS((divisor)-1))
This invokes a couple of macros in kinetis.h:

Code:
#define SDHC_SYSCTL_SDCLKFS(n) (uint32_t)(((n) & 0xFF)<<8) // SDCLKFrequency Select
#define SDHC_SYSCTL_SDCLKFS_MASK ((uint32_t)0x0000FF00)
#define SDHC_SYSCTL_DVS(n) (uint32_t)(((n) & 0xF)<<4) // Divisor
#define SDHC_SYSCTL_DVS_MASK ((uint32_t)0x000000F0)
The problem is that the code is feeding the prescale value (a single bit set in an eight bit field) to the divisor macro (four bits) and the divisor value to the prescale macro. The result is clock frequencies are set to values that aren't predictable since operation with more than one bit set in the prescaler field is undefined.

A simple change fixes it:
Code:
#define SDHC_SYSCTL_DIVISOR(prescale, divisor) \
(SDHC_SYSCTL_SDCLKFS((prescale)>>1)|SDHC_SYSCTL_DVS((divisor)-1))