Hi,
I think I found the real root cause of the issue. For a Teensy 3.5 at 72 MHz or above the 100ns Hold-up time for NSS after the falling edge of the SCK line is not adhered to. At 72 MHz the timing margin is too narrow, at 96 and 120 MHz NSS rises high already when SCK is still high. For details see attached.
A workaround is described as well.
Something nice with a real defined delay at the end of the last spi clock cycle is a bit too much for my current coding skills within these myriad of files.
But I might get there.
Pim
I think I found the real root cause of the issue. For a Teensy 3.5 at 72 MHz or above the 100ns Hold-up time for NSS after the falling edge of the SCK line is not adhered to. At 72 MHz the timing margin is too narrow, at 96 and 120 MHz NSS rises high already when SCK is still high. For details see attached.
A workaround is described as well.
Something nice with a real defined delay at the end of the last spi clock cycle is a bit too much for my current coding skills within these myriad of files.
But I might get there.
Pim