Possible to get some use out of Flexbus on teensy 3.6?

[Blackaddr]

I want a high throughput interface to an FPGA that will act as a co-processor for doing FFTs. I could use multiple SPI busses but I'd rather try to get something going with Flexbus.

I've done some searching on Flexbus and I think Paul already said it's a no-go because certain pins are not broken out.

I checked the K66 datasheet as well as the Teensy 3.6 and it looks like the 'deal breakers' missing pins are
FB_TA (transfer acknowledge)
FB_TBST (burst transfer)
FB_TSIZ;1:0]
FB_BWEn
FB_CSn (for n != 0)

The following are present though:

FB_AD[19;0]
FB_CLK (via CLKOUT)
FB_CS0
FB_RWb
FB_TSb
FB_OEb

I'm speculating that you can still get a partial Flexbus working (up to 1 Mbyte addressable memory space with 20 address bits), but you will be restricted in how you use it. A driver would need to enforce these restrictions.

Mitigating the unavailable pins:

FB_TA/FB_ALE - with auto-acknowledge mode, I think this pin is not required.
FB_TBST - if we restrict ourselves to only burst mode, or non-burst mode, we can control this with a GPIO (or even tie it off on the slave). We would lose the ability to assign burst-mode on a transaction-by-transaction basis since the signal will be psuedo-staticly controlled.
FB_TSIZ - This would be controlled psuedo-statiicaly by GPIO as well, meaning all transactions must be exactly the same burst size as configured by these GPIO pins.
FB_BWEn - We would tie these off to indicate no byte-masking. For an 8-bit interface this is no problem, it's not needed anyway. For a 16-bit interface the driver would need to allow only transactions that are a multiple of 2 bytes in size to ensure no masking is required.

So, with some tight constraints on burst-mode and transaction size, I'm thinking there is enough critical signals broken out to get some use out of the Flexbus.

What am I missing?

 

[qix67]

Hi,

I also think it is possible to use part of it and application note AN4393 gives examples using only the pins you gave.

You made a little error, FB_ALE is available (D0 = pin2)

IMHO, LCD example is clearly ok because it uses only FB_CLK, FB_AD[0-15], FB_AD16, FB_RWb, FB_OEb and FB_CSx (CS0 here). I am currently developping uVGA library and I successfully display image using only FB_AD[0-7].

Doing the MRAM example (8 bit data bus, 20 bit address bus, multiplexed mode) also seems ok, it uses FB_CLK, FB_AD[0-18], FB_ALE, FB_RWb, FB_OEb and Fb_CSx (CS0 here). I also agree FB_TA can probably be ignored it the other device on the bus supports this (fast enough? or add wait-state).

I don't know if it is possible to use FB_AD16 and FB_AD17. During my test, I switch pin0 and 1 to alternate function 5 (FB_AD mode) but strangely Serial still works after this. It remains possible to use non-contiguous address range (64KB with ram, 192KB without RAM, and repeat) by wiring FB_AD18+ (K66) to A16+ (memory side).

Due to the missing FB_TSIZ[1:0], the only possible combinations are (IMHO): 8bit data bus w/ byte access, 16 bit data bus w/align access only (=2 bytes or more access on even address). Unaligned access on path bigger than 8 bit requires these signals (see K66 reference manual, "flexbus signal descriptions" table, FB_TSIZ[1:0] line).

From my point of view, The main problem is the number of pins required to wire a 1MB address space, 20 for data & address + 5 utility signals. It is perhaps possible to gain one pin, FB_OEb looks like NOT(FB_RWb) | FB_CS0.

 

[qix67]

Teensy 3.6 with SRAM on flexbus

Just for fun, here is my first prototype of teensy with additional 512KB. Only 64KB are wired here because the next 2 address pins are Serial1 pins.

The prototype works... randomly. I currently can see 2 reasons, the address latches are too slow or the signals are too noisy (why, the board is so clean , I just used all my wires to make it)


SRAM is connected with a 16-bit data, only 16-bit aligned 16-bit access are possible.

 

[Blackaddr]

Haha, that's awesome, but at least it's a start!