This question depends on what you mean by "accurately". You haven't mentioned the frequency range or level of precision required.
The main issue with preserving PWM duty cycle as you convert to different voltage ranges is matched behavior for both rising and falling edges. Most CMOS logic families have similar propagation delay and similar low-to-high and high-to-low transition times for their output drivers. But ancient TTL logic, some modern BiCMOS chips, and circuits built from optocouplers, transistors, opamps, diodes and resistors often do not have similar performance for rising and falling edges. Either mismatched delays or different rise vs fall speed of the circuit's output can alter the duty cycle.
But like most engineering questions, the question becomes a matter of tolerance & design requirements/margins. Real circuits are never perfect. What is considered good vs poor really depends on your specific frequency and accuracy requirements, which weren't giving in this question.