Teensy 3.6 5V PWM Signals

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christeensy

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Hi all,

Since Teensy 3.6 pins are not 5V tolerant, I was wondering what I can use to still accurately detect both 3.3V and 5V PWM signals at high frequencies.
Apologies if this has been asked before.

Thanks!
 
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1) PWM signal -> 4k7 resistor -> base of a 2N3904 transistor -> 2k2 resistor -> ground.
2) emitter of the 2N3904 -> ground
3) Connect the collector of the 2N3904 via 3k3 resistor to +3.3V and to the Teensy's input.

That's the easiest way to handle input signals with varying levels. The logic levels (HIGH/LOW) will be reversed, but that can easily be handled in code (i.e. trigger on RAISING instead of FALLING).
 
This question depends on what you mean by "accurately". You haven't mentioned the frequency range or level of precision required.

The main issue with preserving PWM duty cycle as you convert to different voltage ranges is matched behavior for both rising and falling edges. Most CMOS logic families have similar propagation delay and similar low-to-high and high-to-low transition times for their output drivers. But ancient TTL logic, some modern BiCMOS chips, and circuits built from optocouplers, transistors, opamps, diodes and resistors often do not have similar performance for rising and falling edges. Either mismatched delays or different rise vs fall speed of the circuit's output can alter the duty cycle.

But like most engineering questions, the question becomes a matter of tolerance & design requirements/margins. Real circuits are never perfect. What is considered good vs poor really depends on your specific frequency and accuracy requirements, which weren't giving in this question.
 
Ahh I see, that explains a lot! Thank you for the detailed response.

I am looking at applications in the frequency range 10kHz to 400Khz. I guess that is a wide spectrum, but are there recommended CMOS chips for these ranges?
In terms of accuracy required, I guess it would be nice to measure a 70% duty cycle with +- 1% accuracy.

PaulStoffregen said:
Either mismatched delays or different rise vs fall speed of the circuit's output can alter the duty cycle.
Click to expand...

Yeah, I am tempted not to use them for quadrature encoders for example as they depend on an exact phase difference.
 
1% of 400 kHz is only 25 ns. If you use FTM timer input capture, the timers can resolve this when running at 48 or 60 MHz. But you probably can't achieve this level of precision with software-based techniques that involve interrupt latency.

Of course, whatever hardware converts the signal need to preserve the edges to better than 25 ns. I'd go with a 74LCX logic family chip.
 
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