SPI with simulated chip select

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WMXZ

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I'm facing the following problem
I wanted from my T3.2 to access 3 SPI devices (ADS1282 ADCs), that do not have a ChipSelect (better, I could not find them)
The ADCs are running continuously, so reset/sync/powerdown are not an option.

I need the chip select for selectively writing to / reading from the different devices.

So my thought is to add a 2 to 1 mux onto the clock line (one input connected to SPI clock, other input grounded)
This way; I need only a single mux for each ADC.

My question to experts is:
considering typical Teensy SPI clock speed
- are there better ways for a T3.2?
- I found 74LVC1G3157, which seems to do what I wanted, but is for analogue signals, would that be suited for digital signals? Are there alternatives?

thanks
Walter
 
FrankB did a memory board for SPI Flash that would allow selecting from a few live chips. He published note here and board on OSHPark - including the BOM.

Had something to do with these:
74LCX126MXCT-ND IC BUFFER QUAD LV N-INV 14SOIC MEMBOARD 3 0 0.49000 1.47
74LCX138MXCT-ND DECODER/DEMUX 1-OF-8 LV 16SOIC MEMBOARD 3 0 0.53000 1.59
 
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So, one option could be to use an SN74AHCT126, which is a 4-buffer package with output enable pins.
You'd tie your clock pins to the input of each of the buffers, with the outputs going to the SPI devices. The use the enable pins as chip select pins. Buffers with a low logic OE will be tristate and thus disconnected.
 
FrankB did a memory board for SPI Flash that would allow selcting from a few live chips. He published note here and board on OSHPark - including the BOM.

Thanks, that was a good hint (your memory is better than mine)
As I wanted to have the MUX on the ADC, looking for 74LCX138, side I found NC7SZ157 that is a 2:1 UHS non-inverting multiplexer.
 
So, one option could be to use an SN74AHCT126, which is a 4-buffer package with output enable pins.
You'd tie your clock pins to the input of each of the buffers, with the outputs going to the SPI devices. The use the enable pins as chip select pins. Buffers with a low logic OE will be tristate and thus disconnected.
Not sure how SPI device will react if clock line will be tristate (i.e. no connection)?
 
So my thought is to add a 2 to 1 mux onto the clock line (one input connected to SPI clock, other input grounded)
This way; I need only a single mux for each ADC.
You still need a mux for the ADS DOUT.
 
You still need a mux for the ADS DOUT.

Could you elaborate?
My reasoning is, that the ADS clocks the data both in and out once it get the clock signal.
if SCLK is low it does not send data.
But I could be wrong
 
DOUT won't be tristated / high impedance. If there is no clock signal, the ADC will still drive DOUT low. So if you connect multiple DOUTs together, you get a short.
 
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Not sure how SPI device will react if clock line will be tristate (i.e. no connection)?

If you're worried about it, you could use a pull down resistor on the CLK inputs. This would keep them pulled down to GND unless pulled high by the buffers.
 
If you're worried about it, you could use a pull down resistor on the CLK inputs. This would keep them pulled down to GND unless pulled high by the buffers.

Good idea,
will see which method I'm ending up, switch or enabling buffers.
 
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