TDM: how to use all the 16 available channels

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elfarolab

elfarolab

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Hello,

I am using a Teensy 3.6 in a project with 16 audio outputs:

-8 "wave" channels using an Audio codec from Cirrus, the CS42888
-8 LFO channels using an audio DAC (to be determined..)

My goal is to connect both ICs at the same TDM bus (with 2 clock drivers..) and use all the 16 TDM channels of the new TDM objects at 16bits, 44100 Hz.
The Audio library is 16 bits so the new TDM objects provide 16 channels IN and OUT both at 16bits, clock frequency set at 256fs (11.2896MHz).

I was searching through the digikey, TI, Analog Devices and Cirrus Logic websites, I have read several datasheets but I was unable to find a way to make
use of all the 16 channels available at 16 bits, all the ICs I found, at 256fs (11.2896MHz), divide the data stream in 8 audio channels, 32 bits MSB left justified slots.
There are no doubts about the correct working of an external CODEC connected to just 8 of the 16 channels of the TDM audio library object.
The problem now is how to add another DAC to the same TDM bus and so make use of the remaining 8 channels at 16 bits?

Any idea?

I was thinking at some alternative approaches to use the remaining 8 channels splitting the 32 bits slots in 2 parts and considering just the right part, 16 bits right justified.
I was also imaging a bits shifting to the left after the codec and attach a DAC configured to read a standard TDM but how to deal with the clocks signals going out of sync..

Questions (consider TDM at 256fs, 44100 freq):

-Are there any audio DACs on the market that split the TDM 32 bits slots in 2 X 16 bits and can be configured to read the data to convert from any of the 16 "subslots"?
-Do you have any alternative ideas about how to effectively use all the 16 TDM channels?

Thank you! I appreciate any help.
 
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I believe Texas Instruments has some stereo TDM chips which can be configured to consume any 16 bit position within the stream. Those are the only TDM chips I've seen which can use only 16 bit slots. So far they're untested, but ought to work. When I looked at their datasheet some time ago, it seemed the FS pulse might be 1 bit later than normal TDM.

When I looked at one of those TI parts, it didn't seem to have any pins for I2C address config. You might need an 8 way I2C mux to configure 8 of those chips.

The other crazy alternative would be tristate buffers and logic circuitry to connect two CS42448 chips, where you delay the FS pulse by 16 bits to one chip, and alternately enable the buffers every 16 clocks.

Yet another crazy idea would be dual TDM, for 32 bit inputs and outputs. I believe this should be possible, using the 2nd I2S data pins. Maybe?
 
Thank you Paul for the fast answer,
at the moment I am thinking to just reduce the channels at 4 codec + 4 DAC, 8 in total.
I will explore the audio library and I will try to enable the second I2S bus hardware into the code, my concern about this is the eventual extra overhead and resources consumption but everything need to be tested and determined still.

Thank you! Great work the audio library.
 
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Hello, spending few hours more in searching this morning, I eventually found a 16CH DAC with "TDM16" (..?) support from Analog Devices:

http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1966A.pdf

At page 22 of the PDF DS, there is a timing reference table but it is not clear to me if the device effectively split the standard TDM formatted slot (32 bit slots) in 2 to allow receiving 16 X 16 bit words.
It seems to be compatible but fig. 20 at page 22 is not very clear to me. If I am not wrong, the DLRCLK is the clock signal that does run at 44100Hz, into the same table I see the first step of the bitclock (11.2896MHz)
is always skipped at the beginning of the next 16 bit word.

Please guys, could you help me to understand if this DAC chip is compatible with the audio library? Are the 16 TDM channels possible with this converter IC?
and in case I am right above, how to implement into the library such skipping of the first rising edge of the DBCLK clock?

Thank you so much, I appreciate any help.
Good audio hacking to everybody here.
 
Hello Paul, yes, in case I find a compatible DAC converter, I am going to layout a PCB with that DAC IC in the next week.

It also looks to me compatible, at page 33 for instance, into the table 33, you can set the size of the word:

DAC CONTROL 2 REGISTER
Address: 0x08, Reset: 0x06, Name: DAC_CTRL2
4th bit set to 1 correspond to 16 BCLK cycles/channel slot.

I will implement all the required low pass filters in output, amplification and proper separation between digital and analog GND.

The only doubt for me is at software level, how to code that skipping of the first rising edge of the bit clock?
I saw this feature in other converters as well, so maybe I would like to parametrize that setting of the TDM objects in the audio library, I can code it but I just need an advise where to look to implement it.

Thank you!
 
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Hello,

To add support for the skipping of the first rising edge of the clock bit, I suppose I should work at this file:

https://github.com/PaulStoffregen/Audio/blob/master/output_tdm.cpp

(LOCs: 198-205)
"""
I2S0_TMR = 0;
I2S0_TCR1 = I2S_TCR1_TFW(4);
I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
| I2S_TCR2_BCD | I2S_TCR2_DIV(0);
I2S0_TCR3 = I2S_TCR3_TCE;
I2S0_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
| I2S_TCR4_FSE | I2S_TCR4_FSD;
I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
"""

and insert a parameter there, I am looking into the K66 family datasheet:

http://www.nxp.com/assets/documents/data/en/data-sheets/K66P144M180SF5V2.pdf

Section: 61.4.1 SAI Transmit Control Register (I2Sx_TCSR) page 2115 (real PDF page 2125)
but I can't find the settings to use..

Any better idea or hints?

Thank you!
 
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elfarolab said:
The only doubt for me is at software level, how to code that skipping of the first rising edge of the bit clock?
I saw this feature in other converters as well, so maybe I would like to parametrize that setting of the TDM objects in the audio library, I can code it but I just need an advise where to look to implement it.
Click to expand...
I seriously doubt an extra clock cycle is required. You just need to switch the word clock one cycle early (while the last bit of the previous frame is sent), just like I2S. I2Sx_TCR4 / I2S_TCR4_FSE does that.
 
Hello,

http://www.nxp.com/assets/documents/data/en/reference-manuals/K66P144M180SF5RMV2.pdf

page 2122 (real PDF page 2132) describes the FSE flag, 4th bit of the I2Sx_TCR4 register:


Frame Sync Early
0 - Frame sync asserts with the first bit of the frame.
1 - Frame sync asserts one bit before the first bit of the frame.

So, I should put a 1 there..

This is further explained at page 2142 (real 2152):

61.5.4 - Frame sync configuration
...
• Assert with the first bit in frame or asserts one bit early
...

OK, I will try that and report. Any other else with other suggestions or ideas?

Thank you! I appreciate.
 
elfarolab said:
Any other else with other suggestions or ideas?
Click to expand...

I know this may sound shocking, but perhaps first just try the TDM code as-is, without any of these modifications. I already pulses FS 1 cycle before the first MSB data bit, as shown in figure 20. Odds are very good it will "just work". I'd recommend relaxing for now, at least on this detail.

Also, when you say "page 2142 (real 2152)", I have no idea what you mean. The PDF has only 52 pages, not a couple thousand.
 
Oh, look, they just this month made rev 3. We've been using rev 2 up to this point, but otherwise yes that's the right info. The noise detection features of touch sensing looks like the only significant update. Well, that and they've replaced the old Freescale logo with NXP.

Here's the datasheets page with just the ones used by Teensy.

https://www.pjrc.com/teensy/datasheets.html
 
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