TelephoneBill
Well-known member
I have a specific query about the operation of a PIT (Periodic Interval Timer) on Teensy 3.1. I have read the reference manual but it does not give detail about this query. I wonder if anyone has researched this issue and can provide a definitive answer.
PIT timers appear relatively simple. You load a 32 bit value and when enabled, the PIT will decrement the counter using the peripheral clock. When it reaches zero, it creates a trigger event and sets the "Timer Interrupt Flag (TIF)". In the corresponding Interrupt Service Routine (ISR), it is customary to clear the TIF flag, which then resets the flag and enables another timer interrupt (at the end of a second timing period). The timer will begin that second timer period - but at which instant it begins decrementing is not entirely clear.
The reference manual is clear that it will automatically reload the 32 bit value on reaching zero, and that is before the TIF flag has been cleared.
So my query is - "Does it wait for the TIF flag to be cleared before it begins decrementing the second/next period ?" - or "Does it decrement the counter on the next peripheral clock pulse after it reloads the 32 bit load value (and that is before the TIF flag is cleared)".
The difference between these two possibilities could be important for precision timing of a "repeating" periodic interval. If it waits for the TIF flag to be cleared, then the time required to execute the start of the ISR routine will be included in the overall period timing (and that will accumulate on repeating timing) so clearing the flag should be the first thing that the ISR does. If it is the alternative, then the timing period will depend only on the accuracy of the peripheral clock, and there is a little leeway on when the TIF flag should be cleared.
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Update: Managed to answer my own question after a bit of thought...
I put a "read current value" (PIT_CVAL0) statement as the first line of the ISR (1), then again after a little delay (2), then again after resetting the TIF flag (3). My load value was initially 60000, and the value for (1) was 59987, for (2) was 59951, and (3) was 59943.
This is good news, for it means that the counter decrements on the next peripheral clock pulse even if the TIF flag has not yet been reset. Thus, the timer is not dependant on the CPU code execution or the ISR code.
PIT timers appear relatively simple. You load a 32 bit value and when enabled, the PIT will decrement the counter using the peripheral clock. When it reaches zero, it creates a trigger event and sets the "Timer Interrupt Flag (TIF)". In the corresponding Interrupt Service Routine (ISR), it is customary to clear the TIF flag, which then resets the flag and enables another timer interrupt (at the end of a second timing period). The timer will begin that second timer period - but at which instant it begins decrementing is not entirely clear.
The reference manual is clear that it will automatically reload the 32 bit value on reaching zero, and that is before the TIF flag has been cleared.
So my query is - "Does it wait for the TIF flag to be cleared before it begins decrementing the second/next period ?" - or "Does it decrement the counter on the next peripheral clock pulse after it reloads the 32 bit load value (and that is before the TIF flag is cleared)".
The difference between these two possibilities could be important for precision timing of a "repeating" periodic interval. If it waits for the TIF flag to be cleared, then the time required to execute the start of the ISR routine will be included in the overall period timing (and that will accumulate on repeating timing) so clearing the flag should be the first thing that the ISR does. If it is the alternative, then the timing period will depend only on the accuracy of the peripheral clock, and there is a little leeway on when the TIF flag should be cleared.
===
Update: Managed to answer my own question after a bit of thought...
I put a "read current value" (PIT_CVAL0) statement as the first line of the ISR (1), then again after a little delay (2), then again after resetting the TIF flag (3). My load value was initially 60000, and the value for (1) was 59987, for (2) was 59951, and (3) was 59943.
This is good news, for it means that the counter decrements on the next peripheral clock pulse even if the TIF flag has not yet been reset. Thus, the timer is not dependant on the CPU code execution or the ISR code.
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