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Thread: Suggest next Teensy with Cortex M7

  1. #151
    The pin 11 and 13

  2. #152
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    SPI1 pins could be relocated if needed, but pins 11 and 13 belong to SPI0 :P

  3. #153
    Eng:
    yes I meant the first bus spi so the 0, not the 1. it should move the pin 11 and 13 teensy audio, I do not know if it is possible, and even if we could it should make changes in the audio library. I do not know how to do it

    Fra:
    oui je voulais dire le premier bus spi donc le 0, pas le 1. il faudrait donc déplacer les pin 11 et 13 du teensy audio, je ne sais pas si c'est possible, et même si on le pouvais il faudrait faire des modifications dans la libraire audio. Je ne sais pas commen le faire

  4. #154
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Armadafg View Post
    I do not know how to do it
    All of the audio library examples with SD card show how to assign the SPI pins.

    For example, from WavFilePlayer.ino (in Arduino, click File > Examples > Audio > WavFilePlayer)

    Code:
    // Use these with the Teensy Audio Shield
    #define SDCARD_CS_PIN    10
    #define SDCARD_MOSI_PIN  7
    #define SDCARD_SCK_PIN   14
    
    // Use these with the Teensy 3.5 & 3.6 SD card
    //#define SDCARD_CS_PIN    BUILTIN_SDCARD
    //#define SDCARD_MOSI_PIN  11  // not actually used
    //#define SDCARD_SCK_PIN   13  // not actually used
    
    // Use these for the SD+Wiz820 or other adaptors
    //#define SDCARD_CS_PIN    4
    //#define SDCARD_MOSI_PIN  11
    //#define SDCARD_SCK_PIN   13

  5. #155
    Eng:
    I use the teensy internal sd port. My problem is effectively not the spi port of the teensy audio but the pins 11 and 13 which is used for the sound and which prevents me from using the spi0. spi0 used by the ft81x

    Fra:
    j'utilise le port sd interne du teensy. Mon problème n'est effectivement pas le port spi du teensy audio mais les broches 11 et 13 qui son utilisé pour le son et qui m'empêche d'utiliser le spi0. spi0 utilisé par le ft81x

  6. #156
    Senior Member PaulStoffregen's Avatar
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    Using pins 7 & 14 rather than 11 & 13 is easy. From the example:

    #define SDCARD_MOSI_PIN 7
    #define SDCARD_SCK_PIN 14

    SPI.setMOSI(SDCARD_MOSI_PIN);
    SPI.setSCK(SDCARD_SCK_PIN);

    Then SPI will not use pins 11 & 13, so you can use pins 11 & 13 for audio.

  7. #157
    eng:
    Sorry I think we did not understand each other. Pins 13 and 11 its use by the teensy audio and at the same time I have to use it for the FT 81x because the FT 81x use the bus SPI0

    fra:
    Désolé je crois que l'on ne s'est pas compris. Les pins 13 et 11 son utiliser par le teensy audio et dans un même temp je dois l'utiliser pour le FT 81x car le FT81x utiliser le bus SPI0

  8. #158
    Senior Member+ Theremingenieur's Avatar
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    But who needs an audio shield in a 3d printer?

  9. #159
    Ang:
    my project is not the 3d printer but I need it to finish my project

    Fra :
    mon projet n'est pas l'imprimante 3d mais j'en ai besoin pour finir mon projet

  10. #160
    Senior Member+ Theremingenieur's Avatar
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    Ah, I misunderstood. But, finally, what is your project? I can't remember you having given any details besides of using the audio shield and EVE graphics...

    Seen that FrankB managed to run a full Commodore C64 emulation including driving a TFT display on a single Teensy 3.6, I can hardly imagine what you are trying to achieve and running into limits.

  11. #161
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Armadafg View Post
    Pins 13 and 11 its use by the teensy audio and at the same time I have to use it for the FT 81x because the FT 81x use the bus SPI0
    SPI0 does not require pins 11 & 13. Alternate pins are possible, pins 7 & 14.

    Maybe this picture can help?

    Click image for larger version. 

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    If you use pins 7 & 14 for SPI0, then pins 11 & 13 are not used by SPI0.


    Future Cortex-M7 chips will have similar pin assignment choices, where conflicts are solved by assigning certain functions to non-default pins. This is an important concept to understand now for Teensy 3.x and for future Teensy using Cortex-M7.
    Last edited by PaulStoffregen; 05-17-2018 at 11:46 AM.

  12. #162
    eng:
    Thank you Paul I managed to move the pin 13 and 11 of the FT81x to 7 and 14 . I can not test the teensy audio and the FT81x at the same time for now, but it should work. To use the SPI RAM on the bus SPI1 it will have to be easy but if I want for example uses the WiFi library on the bus SPI2 I should modify it (WiFi library) ?

    fra:
    Merci Paul j'ai réussi a déplacer les pin 13 et 11 du FT81x vers les 7 et 14 . Je ne peux pas tester le teensy audio et le FT81x en même temps pour l'instant, mais ça devrait fonctionner. Pour utiliser la SPI RAM sur le bus SPI1 ça devra être facile mais si je veux par exemple utilise la WiFi library sur le bus SPI2 je devrais la modifier ?

  13. #163
    Senior Member+ Theremingenieur's Avatar
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    @Armadafg: I think you should open a new thread to get help with your current project. It's ways off topic here.

  14. #164
    eng:
    it's true you're right

    fra:
    c'est vrais vous avez raison

  15. #165
    eng:
    To come back to the subject of teensy 4 I do not think there is a perfect teensy. There is more than one request diffrenent.

    This is why we should make several different size and different prices and this with a clear and precise name. For example, use the following denomination: Teensy XYZ:
    The X would correspond to the generation of Teensy so here 4.
    The Y would correspond to the size: 3 sizes of a teensy 3.2 / 3.1 / lc. 5 = sizes of teensy 3.5 / 3.6 and 7 that for sizes of "Teensy 3.5 / 3.6 Breakout": https://www.tindie.com/products/logl...on-a-standard/.
    And in the end the Z would correspond to the power.

    I know that setting up a whole new range of teensy can be very complex but it can be very intersting


    Fra:
    Pour en revenir au sujet de la teensy 4 je pence pas qu'il y ai une teensy parfaite. Il y a plusier demande diffrenent.

    C'est pour cela qu'il faudrait en faire plusieurs de différente taille et différent prix et cela avec une dénomination claire et précise. Par exemple en utilisent la dénomination suivante : Teensy XYZ :
    Le X correspondrait a la génération de Teensy donc ici 4.
    L’Y correspondrait a la taille :3 tailles d'une teensy 3.2/3.1/lc. 5 = teensy 3.5/3.6 et 7 celui du "Teensy 3.5/3.6 Breakout" : https://www.tindie.com/products/logl...on-a-standard/ .
    Et en fin le Z correspondrait à la puissance.

    Je sais que mettre en place toute une nouvelle gamme de teensy peut etre tres complex mais ca peut etre tres interssant

  16. #166
    Senior Member PaulStoffregen's Avatar
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    Every time we talk of future Teensy models, these same subjects are discussed all over again. Soon we'll probably see talk of finer pitch pins, high density I/O connectors (seems Sony is using this with their new entry to the Arduino market... I held it in my hand yesterday at their booth here at Maker Faire).

    I've said this before, and I'll repeat it again now. A large number of Teensy models is not economically viable for PJRC. The reality is Teensy has only a small portion of the Arduino market. Most people use the less powerful boards (or Chinese clones). With SMT electronics manufacturing, if you make too few of any model, the many fixed costs (both NRE & ongoing) greatly drive up prices or make it a money-losing venture. The pie is only so large and if you try to slice it into too many pieces, they end up too small to be viable.

    We currently make 6 models, two 8 bit and four 32 bit. When we go to Cortex M7, this will expand probably to 8 models. Perhaps it may grow to 9 as more powerful Cortex M7 chips become available. Or it may shrink to 7 when/if the old 8 bit products are eventually discontinued (unlikely before late 2019 to 2020).

    The other reason to limit the number of models is software support. I try very hard to give everyone a great user experience while supporting powerful features that almost all the other Arduino compatible makers feel are too difficult or involve too much cost to develop or support. This is only possible if we limit the number of models. More hardware models to support greatly multiplies the difficulty of providing a good user experience.

    It's easy to imagine a huge range of products. It's also easy to fantasize about huge (or unsustainable) funding and far more than 24 hours in every day! But the practical reality is Teensy's product line is constrained by the economic reality of a small company making these boards at modest volume, and by the finite number of hours in every day to do all the work to actually develop and support them well.

    When we introduce Cortex M7 based models, which *will* happen but currently does not have a solid time-frame, there will be at most 2 new models.

  17. #167
    Member dauntless89's Avatar
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    Your community support is remarkable and appreciated, and I am definitely looking forward to the new Teensy(s).

    Are you far enough along yet to have an idea whether or not the T3.6 form factor can be retained?

  18. #168
    Senior Member+ defragster's Avatar
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    Indeed there is a parallel thread about alternate variations - and it has this note about two potential directions for PJRC - here is a clipped version from Paul

    Quote Originally Posted by PaulStoffregen View Post
    ... I will risk mentioning I'm leaning towards two possible paths on the form factor. One way would look like 2 different products, mimicking the Teensy 3.2 form factor as closely as possible with the cost as low as we can manage, with the second higher cost board having a "long" form factor (maybe Teensy 3.6 pinout, maybe longer) and provisions built in for all sorts of I/O. ...

    Again, this is all still *very* early. Expect this all to take a very long time. It will feel like vapor! ...

  19. #169
    Member dauntless89's Avatar
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    Reviewing the 1050 datasheet, it says:

    Linear successive approximation algorithm with up to 12-bit resolution with 10/11
    bit accuracy
    Am I correct in interpreting this to mean the 1050's ADC is technically 12-bit, but only 10/11 are useful like the 3.6 is technically 16-bit, but only 13-bits are useful?

  20. #170
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by dauntless89 View Post
    Reviewing the 1050 datasheet, it says:

    Am I correct in interpreting this to mean the 1050's ADC is technically 12-bit, but only 10/11 are useful like the 3.6 is technically 16-bit, but only 13-bits are useful?
    Probably generally right - there have been notes about the minimized analog capabilities of the MCU in use. No DAC and more limited ADC resolution. When the clock is 600 MHz and I suppose the die parts are smaller than previous generations it seems that results in lesser Analog capabilities it what appears to be an MCU at less than half the cost of a K66 (though requires external Flash) . Paul posted some details on the K66/K64 fabrication in the last Teensys - if that were done on the 1050/1052 for the T_4 I suppose it would explain the silicon compromise made for manufacturing it.

  21. #171
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    Not sure I saw this 1/10/2014 post before - it isn't the more recent one - 2 years old now? - May have found it again below - but it touches on the design constraints in making an MCU work - and explains why the T_4 MCU has bulk off chip Flash - why the Analog is limited as the 600 MHz core needs a lot more support cache to keep from stalling - which is okay as long as the 'parts' shrink it can expand the cache and add cool features like this because the core is running about twice as fast as external storage:
    The processor has an in-order super-scalar pipeline by which many instructions can be dual-issued, including load/load and load/store instruction pairs because of multiple memory interfaces.
    Quote Originally Posted by PaulStoffregen View Post
    The reason "why" has to do with trade-offs in the actual silicon fabrication processes.

    On Teensy, the processor, RAM and non-volatile storage is all on the same piece of silicon inside a single chip. The silicon can't be overly optimized for any one thing, but rather a balance that achieves overall performance for all 3.

    On Raspberry Pi, the processor, RAM and non-volatile storage are separate chips. Each piece of silicon can be highly optimized for its specific task. The Broadcom BCM2835 processor on the RPi actually has a memory chip stacked on top of it, so the 512M RAM is separate silicon optimized for memory density (and would probably only be able to implement a 1980-era processor). Some other "single chip" SoC boards actually have 2 pieces of silicon mounted inside 1 plastic package. On a RPi, the non-volatile storage in the SD card is probably also 2 pieces of silicon, one optimized for high density flash and a small controller chip.

    The key point, the reason why, involves dramatically optimizing the silicon fabrication for a particular purpose, at the expense of other applications. There are people who are truly experts in this silicon fab stuff. I'm not one of them. This is only my general knowledge. Someone who really does this stuff could speak much better about the specific silicon trade-offs (expect much of this stuff is closely guarded trade secrets of some of the world's most powerful companies). But here's some very general ideas....

    Flash memory's dual gate requirement has traditionally been the big speed-limiting issue in silicon fabrication. Normal CMOS fabrication requires only 1 thin oxide layer to separate the gates from the chip's substrate, and it only needs to insulate well enough for the transistor to work at relatively slow clock speeds. In flash memory, 2 thin oxide layers are needed. The non-volatile storage is achieved by trapping electrons on a floating transistor gate between the oxide layers. Each layer needs to insulate extremely well, since those electrons are supposed to remain trapped there for over 100 years at room temperature.

    Silicon fabrication is done in layers, usually be growing an oxide layer (pure glass) on top of the wafer plus everything done in the previous steps. The a photosensitive mask chemical is added and exposed to light through the masks that define where the circuit feature will be. The wafer is then exposed to a strong acid that etches away the oxide (glass) where the mask allowed light. Then the wafer is coated with other stuff and baked at very high temperature, causing that stuff to become part of the chip (eg, "stuff" can be materials the implant into the silicon itself, or grow more layers on top of remaining oxide that may itself be on top of other layers). Then more acid or other chemicals remove the excess stuff, the resist and unneeded oxide. This is repeated many times, building up the many features and layers inside the chip, starting with the N+ and P+ implants that form the source and drain of transistors, then the "polysilicon" layers that form the transistor gates, and finally metal layers for signal routing.

    One pretty incredible challenge in this fabrication process is not destroying the work from all the previous layers. My understanding is the general approach involves using progressively lower temperatures for each step. The upper layers tend to have lower resolution and other limitations. The entire process is really a pretty marvelous achievement of modern technology. But it's far from magic. There are a LOT of difficult tradeoffs.

    Those tradeoffs can be made in many different ways, which can optimize the process for a particular application, but too much optimization for one thing can cause that silicon fab to be nearly useless for others.

    Flash memory's requirement for floating gates apparently imposes a lot of limitation on all the other layers that can be fabricated inside the chip. Again, there are poeple who really know the details, but I sadly only have general knowledge in this area. I've been told DRAM processes involve multiple layers of polysilicon, which has high resistivity (slow circuit speeds) but can be made with incredibly fine resolution and is made at much higher temperature. For designing logic circuits that run at high speed, you generally want to connect the polysilicon gates to low impedance metal routing as closely as possible, since the gates are capacitive. There are a LOT of trade-offs in these silicon processes.

    So that's why. On Teensy and all flash-based microcontrollers, the silicon is optimized for balance to achieve performance. You get logic circuitry, volatile and non-volatile memory all on the same piece of silicon, but it can't be too heavily optimized for any one of those things without sacrificing performance on the others. The on-chip flash memory imposes a lot of restraints on the silicon design. You also tend to get fairly low power, because everything is on the same chip, and also because the optimizations for flash memory tend to be similar for the optimizations for low power.

    Even though Raspberry Pi might be called a SoC (System on Chip), in reality it's separate chips for the CPU+GPU and the DRAM, where the Boardcom chip is highly optimized for fast logic circuitry and the DRAM chip on top is optimized for dense volatile memory. Inside the SD card, there's a high density flash chip (or stack of such chips in the larger cards) fabricated on a silicon process that's optimized for flash only. In fact, NAND flash is so optimized for density that a small percentage of the sectors are bad and more defects develop over time, so SD cards have a small controller (fabricated on different silicon) that manages the media defects and performs wear leveling. Extremely optimized NAND flash might not even retain data for 10+ years, since the controller makes heavy use of error detection and correction algorithms and automatically reassigns data to new areas of the media as defects develop. They don't tell you such things when you buy a 32GB card at a retail store, but internally that capacity is made possible by these types of extreme optimizations.

    This turned out really long, but hopefully that gives you a better idea of why the market is filled with 2 different classes of products.
    This may be the post from 2016 that adds some detail:
    Quote Originally Posted by PaulStoffregen View Post
    A finer point of IC manufacturing that's not often spoken is the incredible specialization of modern fabrication processes. You can see press releases that nVidia is using a 16 nm TSMC process for their new GPU chips and they'll use Samsung's new HBM DRAM made (maybe) with 29 nm silicon. Similar statements can be regularly found regarding NAND flash memory. If any technical info is given at all, it's the transistor channel length. Anyone reading only this info could easily believe they're all very similar.

    What's rarely mentioned, especially in these modern times where companies consider even fairly obvious facts to be closely guarded proprietary trade secrets, is the incredible difference between these silicon processes. DRAM memory, for example, requires memory cells which are basically a mosfet transistor where the gate capacitance holds the data. Tricks are played with a DC offset voltage on the entire area of the chip holding these transistors, to reduce the effective voltage that's trying to pull these precious few electrons off the transistor gates. The insulating layer on the gate is made differently, to reduce the leakage, but that also changes the transistors switching threshold voltage. Since most of the chip is just these cells and row/column access lines, relatively few metal layers are needed for wires.

    Likewise, those TSMC processes for logic circuits are heavily optimized for fast digital circuitry, but at the expense of other stuff. You can't implement flash memory at all, and high accuracy analog circuits (like the ADC and DAC on Teensy) are pretty much impossible. SRAM can be made using 4 or 6 transistor cells, but it's very expensive.

    MCUs are typically made with 90 nm or larger transistors. Soon we'll start to see 65 nm being used, but there are huge challenges getting flash memory to work reliably. The 90 nm (and larger) processes allow for a good balance of features, so you can have reliable flash memory, RAM and pretty good logic speed, and fairly accurate analog circuits (at least well matched capacitors) all on the same piece of silicon. But at 90 nm, every extra feature takes quite a bit more silicon area than adding stuff on the most advanced logic-only chips.

    Perhaps we'll eventually see 45 nm and even more advanced processes able to implement single-die MCUs. Maybe? Or perhaps designs similar to the ESP, where a separate flash chip is used for non-volatile memory, will become the norm?

    One thing is pretty certain to remain the same. Silicon process for the fastest logic, best DRAM, and best Flash will continue to be very different. Adding extra logic-only features to the logic die may be cheap, if those features don't require adding memory or analog features. But the higher the silicon performance, the more specialized the process must be, which means adding extra features that silicon isn't meant to implement is very difficult and expensive.

  22. #172
    Senior Member+ Theremingenieur's Avatar
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    Since the nude silicon dies are incredibly small, there is no reason for not assembling different dies with different channel lengths and optimizations in one single IC housing.

    Afaik, there exist codec ICs which combine 120dB SNR 24bit 96kHz AD/DA with powerful 32/64bit DSP computing for up to 8x oversampling, filtering, and more, which requires a fair amount of RAM and flash memory, too, which proves that building powerful true mixed signal ICs is definitively possible. That’s why I still can’t understand why the analog I/O of the KINETIS MCUs doesn’t keep up with their DSP power under the hood.

    Designing high end audiophile and musical stuff was mostly about selecting good analog components, biasing everything correctly to obtain decent THD and SNR, and routing/shielding the signals to minimize crosstalk, noise and interference, only 20 years ago. With today’s 32bit DSPs, all that is theoretically not longer an issue. Even if the last 6 or 7 bits become insignificant due to rounding errors etc., this will still remain ways below human perception level. So, the designer can nowadays concentrate on the algorithms which allows him to realize even more complex transfer functions in a much more quicker, reliable, and reproducible way in software and he would theoretically not longer have to deal with the tolerances, aging, and other imperfections of analog components.

    That’s the theory. In practice and most times, you simply can’t get the all.in.one.single.chip. There seems no Cortex M4 based MCU with integrated audiophile AD/DA to exist in the market, thus, you have to struggle again as before for finding suitable peripherals, and you have to deal with the I2C/SPI/I2S bottlenecks, although everything could be so simple.

  23. #173
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    Quote Originally Posted by Theremingenieur View Post
    although everything could be so simple.
    maybe because there is no market? And one gets one pays for.

  24. #174
    Senior Member+ Theremingenieur's Avatar
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    If there is no more market for audiophile and true musical stuff because nearly everybody is satisfied with mp3 quality out of class D PWM amps and a few blinking LEDs, that’s the end of the human civilization.

    I’m sounding like a nostalgic old fart, I know. But I am definitively a nostalgic old fart

  25. #175
    Senior Member PaulStoffregen's Avatar
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    Pretty sure consumers listening to recorded music and musicians performing & recording are considered very different markets.

    Nostalgia can be tricky. Only a few decades ago consumers were satisfied by vinyl records and cassette taps (forgetting 8-track & reel-to-reel). Yeah, I know some people have vinyl nostalgia, but the reality was at best 80 dB SNR (often 60 dB or less, especially after some handling), and pretty dismal performance if you factor in distortion.

    Today I would fault cheaply made headphones and speakers (or expensive ones which over-emphasize & even resonate bass) much moreso than lossy codecs and switching amplifiers for the imperfections consumers actually hear.

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