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Thread: Jitter-free DAC output using the FIFO and DMA

  1. #1
    Senior Member
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    Jitter-free DAC output using the FIFO and DMA

    The Audio library uses the PDB to trigger a DMA transfer to the DAC output register. This is achieves low jitter when there is no other DMA traffic. However, other DMA transfers can delay the DAC transfer and result in jitter.

    Here is sample code for DAC output using the FIFO and DMA. The FIFO has 16 entries, but only 8 are useful due to hardware limitations. After the first half of the FIFO is output (4 entries), it is updated with a DMA transfer. The same thing happens after the second half of the FIFO has been output.

    Exact, jitter-free timing is achieved. The DAC takes samples from the FIFO at precise intervals, triggered by the PDB (it is not affected by DMA transfer jitter).

    The code will work for DAC1, if references to DAC0 are replaced. DAC1 has its own DMA trigger, so linked DMA is not required when both DACs are used.

    https://github.com/tni/teensy-sample...c_fifo_dma.ino

  2. #2
    Junior Member
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    As no one has commented I thought I would say how cool this looks!!

    The more I play with Micro Controllers the more I am amazed by what cool little features they have to get round there lack of grunt.

    They can really run rings round OS's when it comes to simple ways to do stuff low latency, with the exception of maths they really run rings round things like pi's!

    Do you think this would work with both DAC's at the same time? I think that's what you are implying or would they jitter each other?

  3. #3
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    Quote Originally Posted by wsfish View Post
    Do you think this would work with both DAC's at the same time? I think that's what you are implying or would they jitter each other?
    Yes, it's going to work fine.

    Look at this:
    https://forum.pjrc.com/threads/45214...l=1#post147943

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