Maybe try reconfiguring the crossbar switch bus master priority levels? The default priority levels are shown on page 417. USB1 has priority level 6, the highest of all.
The RAM is slave port #1. So you should be able to change it by writing to AXBS_PRS1. Maybe try writing 0x05432610, so the DMA controller gets highest priority for slave #1.
Maybe also be worthwhile to write to AXBS_CRS1, to configure the arbitration for slave #1 to park on master #2....
Hi Paul,
unfortunately, that's the case already and does not help.
https://github.com/qix67/uVGA/blob/master/uVGA.cpp#L986
But please read the comment:
Code:
// let's also give the highest priority from DMA to RAM and GPIO in crossbar switch
// master 2 = DMA
// slave 1 = sram backdoor
// slave 3 = GPIO
// when only the CPU requests access, this has nearly no effects
// Kinetis Reference manual says 6 is the highest priority but AXBS_PRSn register description says 0 is the highest
// I assumed 6 is correct but wathever I chose, I see no difference during my test
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
AXBS_PRS1 = 0x05432610; //0x06543021;
AXBS_PRS3 = 0x05432610; //0x06543021;
#elif defined(__MK20DX128__) || defined(__MK20DX256__)
AXBS_PRS1 = 0x00002310; //0x00003021;
AXBS_PRS3 = 0x00002310; //0x00003021;
#endif
// to gain 1 more cycle, when RAM and GPIO port is not used, attach them to DMA and for a fixed priority
// with this tip, DMA gains a lot of time... really a lot due to fact the frame buffer must be copied byte by byte.
// This type of copy waste a lot of bandwidth/time, so much it is not possible to trigger copy using a timer to obtain a more accurate pixel
AXBS_CRS1 = AXBS_CRS_ARB_FIXED | AXBS_CRS_PARK_FIXED | AXBS_CRS_PARK(2);
AXBS_CRS3 = AXBS_CRS_ARB_FIXED | AXBS_CRS_PARK_FIXED | AXBS_CRS_PARK(2);
// when DMA uses RAM, it cannot be stopped... but it should already be the default settings.
AXBS_MGPCR2 = 0x00000000;
// all other masters must wait, even during undefined length burst
AXBS_MGPCR0 = 0x00000001;
AXBS_MGPCR1 = 0x00000001;
AXBS_MGPCR3 = 0x00000001;
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
AXBS_MGPCR4 = 0x00000001;
AXBS_MGPCR5 = 0x00000001;
AXBS_MGPCR6 = 0x00000001;
#endif
// give absolute priority to DMA on SRAM_L and favor DMA on SRAM_U
// this final settings greatly improve pixel sharpness and line stability under heavy graphic load
MCM_CR = (MCM_CR & ~(MCM_CR_SRAMLAP(3) | MCM_CR_SRAMUAP(3)))
| MCM_CR_SRAMLAP(3) | MCM_CR_SRAMUAP(1);
Is it possible that there's a bug somewhere ?
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