Full byte/word read and writes? 3.2

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frax

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Teensy 3.2 current, might upgrade in the future.

Im a little confused when browsing through schematics and source code.

Interfacing with an external static 64k RAM. 16 address bits and 8 data bits.
I would like to do full byte or word write to the pins. I haven't connected the RAM yet I'm flexible on which pins to use.

And thats kinda my problem, which pins/ports? PORTA seems use by a few other things. On PORTB I can only find PTB0,1,2,3,16,17 and 18, where did the rest go?
PORTC has PTC0-11, perfect for writing bytes with + a few bits to control some other stuff.

As for my 16 adress bits, PORTD won't help me right?

TLDR;
How do I do byte writes to C0-7? SSRC?
There isn't 16 bits mapped and easily accessible anywhere right? So, just have to set the bits one by one?

--frax
 
In terms of useful consecutive pins, you have C0 - C7, B16 - B23 and D0 - D7. The port registers are 32 pins / bits, but byte access works. So you could do 3 byte writes for the pins I mentioned to set 16 address bits + 8 data bits.

E.g to set B16 - B23:
Code:
volatile uint8_t* ptb_16_23 = (volatile uint8_t*) (uintptr_t(&GPIOB_PTOR) + 2);
*ptb_16_23 = 0xffu;

EDIT:
That's for Teensy 3.5 / 3.6, for 3.2 you would only have B16 - B19 and B20 - 23 aren't there. With Teensy 3.2, you are out of luck in terms of 3 consecutive 8-bit pin ranges.
 
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As mentioned, you do not have the contiguous ports to do exactly what you desire.

With the 3.2, the largest contiguous configuration is one 12 bit port (C0-11) and one 8 bit port (D0-7).

You will find a visual chart of the 3.2 port mapping and other useful information in this thread: https://forum.pjrc.com/threads/17532-Tutorial-on-digital-I-O-ATMega-PIN-PORT-DDR-D-B-registers-vs-ARM-GPIO_PDIR-_PDOR

A few other items on parallel I/O (as used with TFT LCD's) can be found here: https://forum.pjrc.com/threads/23950-Parallel-GPIO-on-Teensy-3-0

When you are dealing with a microcontroller that has no external parallel memory interface, weighing a possible speed benefit, the additional I/O pin usage plus the code complexity, SPI ram wins hands down over trying to use parallel ram. Ultimately, if ram speed of access is what you're after, just make the $25-$30 investment and buy a 3.5 or 3.6. There is no off-chip solution that has that speed.

If speed isn't front and center and it's just R/W capacity, have a look at SPI based FRAM.
 
Is there some particular reason to use a parallel 64K RAM chip? Really, any reason is ok, even just the desire for a project aesthetic involving lots of wires.

I'm just curious why, since this is so little RAM and at such low performance compared to just stepping up to Teensy 3.5 or 3.6.

If you do get this wired up, please consider the chip's access time. Some RAM chips are quite fast, but a lot of the old ones have slow access times of 100 ns or longer. If you use direct register access, a Teensy 3.2 can drive the CS & RD pins low (after you've set up all the address pins) and then read the 8 bit port faster than the chip's access time. A brief delay might be needed if your RAM chip is an older one with long access time.
 
Super, thanks for all the info, I think I got all I need now :)

Is there some particular reason to use a parallel 64K RAM chip?

Yes, the RAM is not mine, I'm just hijacking it from a Z80 computer by pulling BUSREQ. That way I can read and modify it before returning it to the Z80.
 
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