Teensy 3.x External memory bus feature usability or substitute?

Status
Not open for further replies.
G

gwideman

Well-known member
Hi all, though probably for Paul:

I see that the MCU in the 3.6, (and maybe some <=3.5 ones), has a configuration that allows for an external memory bus, allowing external devices (memory, FPGA) to map to CPU memory space, and for fast I/O to those devices, and presumably DMA too.

Anyhow, I'm curious whether any Teensy 3.x's actually support using this scheme? Is it just a matter of whether the (many!) pins are routed to accessible pins (and do you happen to know if they are)? Or are there other considerations?

And I guess the fallback from that is to configure a simple "parallel port" interface run by software, with say 8 or 16 data lines, some handshake lines, address (if not multiplexed on the data lines) and so on. Am I right that such a scheme is never going to be able to work with DMA?

Thanks, Graham
 
defragster said:
Paul made a note recently, perhaps relevant :
Click to expand...

Hahaha thanks for the link. One way it's relevant is that the Cortex M3/M4 book I bought last week on Paul's recommendation will soon be obsolete. Doh! I knew that would happen.

Anyhow, in that post Paul maybe implies that Flexbus might be usable on 3.5/3.6, so I did a survey of the pins required to do Flexbus, versus the pins routed on those Teensies.

By my accounting, it should be possible to use Flexbus's mode that multiplexes data and addresses on the same lines, for 8-bit and 16-bit widths (using Byte Lane Shift BLS = 1) for both address and data, but not 32-bit width. And I see that Flexbus pins that are not used in a particular application can be multiplexed to their normal other functions, using appropriate settings in the Port Control registers.

An 8 bit or 16 bit (plus a few control-lines) interface to registers in an FPGA or other external chip, that appears in Teensy's address space, would be pretty useful and convenient.

However, I haven't looked in detail to see what features Flexbus displaces.

I did run across what appear to be mistakes in the K64 and K66 manual relating to Flexbus, which I add here in case anyone happens to know the scoop and would comment:

The manual's description and data regarding the plain (not multiplexed) Address Bus FB_Axx seems messed up. K66 Section 34.3 describes it as FB_A31 - FB_A0, whereas K66 section 11.4.4 Memories and Memory Interfaces table shows FB_A[29:16] only. And in section 11.3 Pinouts, only signals 29 to 16 are shown.

It's hard to imagine that a bus would have only signals 16 through 29, but if there are actually signals FB_A0 through FB_A31, then where are they in the pin assignments?

So, not 100% confident in my conclusions about all this at the moment, and would love to hear if someone has tried all this out.
 
Last edited:
Status
Not open for further replies.
Back
Top