Hi all, though probably for Paul:
I see that the MCU in the 3.6, (and maybe some <=3.5 ones), has a configuration that allows for an external memory bus, allowing external devices (memory, FPGA) to map to CPU memory space, and for fast I/O to those devices, and presumably DMA too.
Anyhow, I'm curious whether any Teensy 3.x's actually support using this scheme? Is it just a matter of whether the (many!) pins are routed to accessible pins (and do you happen to know if they are)? Or are there other considerations?
And I guess the fallback from that is to configure a simple "parallel port" interface run by software, with say 8 or 16 data lines, some handshake lines, address (if not multiplexed on the data lines) and so on. Am I right that such a scheme is never going to be able to work with DMA?
Thanks, Graham
I see that the MCU in the 3.6, (and maybe some <=3.5 ones), has a configuration that allows for an external memory bus, allowing external devices (memory, FPGA) to map to CPU memory space, and for fast I/O to those devices, and presumably DMA too.
Anyhow, I'm curious whether any Teensy 3.x's actually support using this scheme? Is it just a matter of whether the (many!) pins are routed to accessible pins (and do you happen to know if they are)? Or are there other considerations?
And I guess the fallback from that is to configure a simple "parallel port" interface run by software, with say 8 or 16 data lines, some handshake lines, address (if not multiplexed on the data lines) and so on. Am I right that such a scheme is never going to be able to work with DMA?
Thanks, Graham