Hi All.
Wondering if anyone has looked at the I2S Microphone breakout module over at Adafruit:
https://www.adafruit.com/product/3421
Datasheet for the device itself is here:
https://cdn-shop.adafruit.com/product-files/3421/i2S%20Datasheet.PDF
The I2S timing for this device looks odd. It expects the WS (aka Frame Sync, aka LRCLK) signal to transition on the falling edge of BCLK while the Data transitions on the rising edge:
This is different than every other I2S device I’ve looked at. The NXP SGTL5000 for example:
I’m not even sure the Teensy 3.2 (MK20DX256) can do this since it looks like the Bit Clock Polarity (BCP) field in the I2Sx_TCR2 register applies to both LRCLK and Data.
Appreciate hearing thoughts on this topic.
Thanks.
PS -- I’ve posted a similar question on the Adafruit forum. No response so far:
https://forums.adafruit.com/viewtopic.php?f=19&t=125101
Wondering if anyone has looked at the I2S Microphone breakout module over at Adafruit:
https://www.adafruit.com/product/3421
Datasheet for the device itself is here:
https://cdn-shop.adafruit.com/product-files/3421/i2S%20Datasheet.PDF
The I2S timing for this device looks odd. It expects the WS (aka Frame Sync, aka LRCLK) signal to transition on the falling edge of BCLK while the Data transitions on the rising edge:
This is different than every other I2S device I’ve looked at. The NXP SGTL5000 for example:
I’m not even sure the Teensy 3.2 (MK20DX256) can do this since it looks like the Bit Clock Polarity (BCP) field in the I2Sx_TCR2 register applies to both LRCLK and Data.
Appreciate hearing thoughts on this topic.
Thanks.
PS -- I’ve posted a similar question on the Adafruit forum. No response so far:
https://forums.adafruit.com/viewtopic.php?f=19&t=125101