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Thread: Teensy 3.6 overclocked to 216-240MHz and audio adapter board -> LRCLK jitter

  1. #1
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    Teensy 3.6 overclocked to 216-240MHz and audio adapter board -> LRCLK jitter

    Hello everyone,

    The facts:

    My current setup is Teensy3.6, arduino 1.8.5, Teensyduino 1.40, osx.
    Compiling for cpu speeds 24-192MHz everything works fine.
    Compiling for 216-240MHz and the audio from the adapter board is distorted.
    You can clearly see the jitter on LRCLK with a scope.
    Audio from the dac is not distorted.
    For those who don't have acces to a scope, I have included a small program to demonstrate the effect.
    You can also use it to compare the outputs of the adapter board and the dac with a scope.

    The questions:

    Is this a hardware limitation due to some kind of clock divider stuff or is it some software problem?
    And how can we solve this?

    The code:

    generate a 4400Hz sine for 2 secs and then sweep to 8800Hz in 4 secs, rinse and repeat.
    Comment everything in the main loop to disable the sweep if you want to compare the 2 outputs on your scope.
    Now compile for 192MHz cpu speed and listen. This is smooth.
    Now compile for 240MHz cpu speed and listen. What is happening?
    Now compile for 216MHz cpu speed and listen. Oh the horror!
    *warning*: your pet(s) may not like this sound.

    Code:
    #include <Audio.h>
    #include <Wire.h>
    #include <SPI.h>
    #include <SD.h>
    #include <SerialFlash.h>
    
    // GUItool: begin automatically generated code
    AudioSynthWaveformSine   sine1;          //xy=71,83
    AudioSynthWaveformSineModulated sine_fm1;       //xy=199,83
    AudioOutputI2S           i2s1;           //xy=370,58
    AudioOutputAnalogStereo  dacs1;          //xy=380,119
    AudioConnection          patchCord1(sine1, sine_fm1);
    AudioConnection          patchCord2(sine_fm1, 0, i2s1, 0);
    AudioConnection          patchCord3(sine_fm1, 0, i2s1, 1);
    AudioConnection          patchCord4(sine_fm1, 0, dacs1, 0);
    AudioConnection          patchCord5(sine_fm1, 0, dacs1, 1);
    AudioControlSGTL5000     sgtl5000_1;     //xy=73,34
    // GUItool: end automatically generated code
    
    void setup() {
    	AudioMemory(2);
    	sgtl5000_1.enable();
    	sgtl5000_1.volume(0.5);
    
    	sine1.frequency(.0625);
    	sine_fm1.frequency(4400);
    	sine1.amplitude(0);
    	sine_fm1.amplitude(1);
    }
    
    void loop() {
    	delay(2000);
    	sine1.phase(0);
    	sine1.amplitude(1);
    	delay(4000);
    	sine1.amplitude(0);
    }

    One final thought, long time ago I once told myself(luckily I didnt swear) I would never use arduino and here I am admitting defeat thanks to Paul's Teensys and audio library.
    Great stuff, thank you very much!

  2. #2
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by neurofun View Post
    Is this a hardware limitation due to some kind of clock divider stuff
    Yes, pretty sure it's a hardware limitation with the I2S MCLK fractional divider. This has come up several times. It's the one part of the chip which really doesn't seem to overclock beyond 192 MHz.

  3. #3
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    Quote Originally Posted by PaulStoffregen View Post
    Yes, pretty sure it's a hardware limitation with the I2S MCLK fractional divider. This has come up several times. It's the one part of the chip which really doesn't seem to overclock beyond 192 MHz.
    It is nor really the overclocking per se, but the 'difficulty' of the chip to generate the clocks for the desired sampling frequency.
    changing the sampling frequency such that the different multiplier and dividers are more 'chip-friendly' (i.e. smaller multipliers) removed the problem in my applications.
    @neurofun, if you need the CPU speed, check the forum on how to change the sampling frequency, say to 48 kHz, or even to som non-standard rate.

  4. #4
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    Thanks for your quick replies. I think I'll be fine for a while @192MHz but it's good to know that I can get more oomph by changing the sample rate.

  5. #5
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    Quote Originally Posted by PaulStoffregen View Post
    Yes, pretty sure it's a hardware limitation with the I2S MCLK fractional divider.
    Good news, it is not. LRCLK is now steady as a rock, compiled at 216MHz and 240MHz.
    Here is the fix for output_i2s.cpp and output_i2s_quad.cpp:
    Code:
    /* fix for LRCLK jitter on Teensy 3.6, neurofun */
    // #elif F_CPU == 216000000
    //   #define MCLK_MULT 8
    //   #define MCLK_DIV  153
    //   #define MCLK_SRC  0
    // #elif F_CPU == 240000000
    //   #define MCLK_MULT 4
    //   #define MCLK_DIV  85
    #elif F_CPU == 216000000
      #define MCLK_MULT 36
      #define MCLK_DIV  153
    #elif F_CPU == 240000000
      #define MCLK_MULT 2
      #define MCLK_DIV  85
      #define MCLK_SRC  0
    /* end of fix */
    Yeah! 25% more oomph for audio applications.

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