Dears,
I want to count the delay in multiplexing ADC modifying this code:
by remplacing ADC0_RA with any count in "micro seconds", I try with RTC_PTR and FTM0_CNT with bus error, there exist some count to make this without bus error?
regards,
Luis
I want to count the delay in multiplexing ADC modifying this code:
Code:
#define ADC_RING_SIZE 0x2000
DMAMEM
volatile uint16_t
__attribute__((aligned(ADC_RING_SIZE*sizeof(uint16_t))))
adc_ring_buffer[ADC_RING_SIZE];
volatile uint32_t adc_config[3] = {
ADC_SC1_ADCH(5), // ADC0_A0
ADC_SC1_ADCH(14), // ADC0_A1
ADC_SC1_ADCH(31), // stop=0b11111=31
}
// enable DMA and DMAMUX clock
SIM_SCGC7 |= SIM_SCGC7_DMA;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
// channels priority
DMA_CR |= DMA_CR_ERCA; // enable round robin scheduling
// configure the DMA transfer control descriptor 2
DMA_TCD2_SADDR = &(adc_config[1]); // ADC0_A1
DMA_TCD2_SOFF = sizeof(adc_config[0]); // Nº bytes between data
DMA_TCD2_ATTR = 0
| DMA_TCD_ATTR_SMOD(0)
| DMA_TCD_ATTR_SSIZE(0)
| DMA_TCD_ATTR_DMOD(0)
| DMA_TCD_ATTR_DSIZE(0);
DMA_TCD2_NBYTES_MLNO = 1; // Nº bytes to be transferred
DMA_TCD2_SLAST = 0;
DMA_TCD2_DADDR = &(ADC0_SC1A); // must be 'nbytes*dsize' aligned
DMA_TCD2_DOFF = 0; // Nº bytes between data
DMA_TCD2_DLASTSGA = 0;
DMA_TCD2_CITER_ELINKNO = 0;
DMA_TCD2_BITER_ELINKNO = 0;
DMA_TCD2_CSR &= ~DMA_TCD_CSR_DONE;
DMA_TCD2_CSR = 0
// disable scatter/gatter processing ESG=0
// ERQ bit is not affected when the major loop is complete DREQ=0
//| DMA_TCD_CSR_MAJORELINK // enable major loop channel to channel linking
| DMA_TCD_CSR_BWC(0) // no eDMA engine stall
// | DMA_TCD_CSR_MAJORLINKCH(2) // major loop channel to channel linking set to 2
// | DMA_TCD_CSR_INTMAJOR // enable the end-of-major loop interrupt
;
// configure the DMA transfer control descriptor 1
DMA_TCD1_SADDR = &([COLOR="#FF0000"]ADC0_RA[/COLOR]); // &(FTM0_CNT); // &(RTC_PTR);
DMA_TCD1_SOFF = 0; // Nº bytes between data
DMA_TCD1_ATTR = 0
| DMA_TCD_ATTR_SMOD(0)
| DMA_TCD_ATTR_SSIZE(1)
| DMA_TCD_ATTR_DMOD(14) // mod = log2(sizeof(adc_ring_buffer))
| DMA_TCD_ATTR_DSIZE(1);
DMA_TCD1_NBYTES_MLNO = 2;// Nº bytes to be transferred
DMA_TCD1_SLAST = 0;
DMA_TCD1_DADDR = &(adc_ring_buffer[0]); // must be 'nbytes*dsize' aligned
DMA_TCD1_DOFF = sizeof(adc_ring_buffer[0]); // Nº bytes between data
DMA_TCD1_DLASTSGA = 0;
DMA_TCD1_CITER_ELINKNO =
DMA_TCD1_BITER_ELINKNO = 1
//DMA_TCD1_CITER_ELINKYES =
//DMA_TCD1_BITER_ELINKYES = 1
// | DMA_TCD_ITER_ELINK // enable minor loop channel linking
// | DMA_TCD_ITER_LINKCH(2) // link to the second channel.
;
DMA_TCD1_CSR &= ~DMA_TCD_CSR_DONE;
DMA_TCD1_CSR = 0
// disable scatter/gatter processing ESG=0
// ERQ bit is not affected when the major loop is complete DREQ=0
| DMA_TCD_CSR_MAJORELINK // enable major loop channel to channel linking
| DMA_TCD_CSR_BWC(0) // no eDMA engine stall
| DMA_TCD_CSR_MAJORLINKCH(2) // major loop channel to channel linking set to 2
// | DMA_TCD_CSR_INTMAJOR // enable the end-of-major loop interrupt
;
// to connect ADC with DMA
DMA_SERQ = 1; // enable channel 1 requests
// configure the DMAMUX so that the ADC DMA request triggers DMA channel 1
DMAMUX0_CHCFG1 = DMAMUX_ENABLE | DMAMUX_SOURCE_ADC0;
by remplacing ADC0_RA with any count in "micro seconds", I try with RTC_PTR and FTM0_CNT with bus error, there exist some count to make this without bus error?
regards,
Luis