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Thread: SPI PCSIS Pin Order

  1. #1
    Junior Member
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    Nov 2017
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    SPI PCSIS Pin Order

    Does anyone know what order the Peripheral Chip Select x Inactive State (PCSIS) order is in?
    Under 57.3 (table 57-5) Module signal descriptions it just shows the PCS0 through PCS5 but it doesn't assign them a bit order in PCSIS.

    Here is a picture to show what I mean
    Click image for larger version. 

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  2. #2
    Senior Member+ KurtE's Avatar
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    PCS0 is the low order bit...
    PCS5 is the highest order bit

    In cases like this sometimes easiest to look at the code that uses it. These are table driven in the SPI code. Example for the T3.1/2... Part of the hardware table:
    Code:
    	10, 2, 9, 6, 20, 23, 21, 22, 15,
    	PORT_PCR_MUX(2),  PORT_PCR_MUX(2), PORT_PCR_MUX(2),  PORT_PCR_MUX(2),  PORT_PCR_MUX(2),  PORT_PCR_MUX(2),  PORT_PCR_MUX(2),  PORT_PCR_MUX(2),  PORT_PCR_MUX(2),
    	0x1, 0x1, 0x2, 0x2, 0x4, 0x4, 0x8, 0x8, 0x10
    The first line is the list of valid CS pins, the 2nd line is MUX values (pin mode) to switch these into SPI mode and the last line is the PCSIS mask bits for them.

    Again FYI if you call SPI.pinIsChipselect(pin_number) it will return this mask.

  3. #3
    Junior Member
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    Nov 2017
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    Thank you very much Kurt, hopefully when my oscilloscope comes in I can just try a configuration and probe the result to save your time =]

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