Does anyone know what order the Peripheral Chip Select x Inactive State (PCSIS) order is in?
Under 57.3 (table 57-5) Module signal descriptions it just shows the PCS0 through PCS5 but it doesn't assign them a bit order in PCSIS.
PCS0 is the low order bit...
PCS5 is the highest order bit
In cases like this sometimes easiest to look at the code that uses it. These are table driven in the SPI code. Example for the T3.1/2... Part of the hardware table:
The first line is the list of valid CS pins, the 2nd line is MUX values (pin mode) to switch these into SPI mode and the last line is the PCSIS mask bits for them.
Again FYI if you call SPI.pinIsChipselect(pin_number) it will return this mask.