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Thread: High PWM frequency with 16 bit accuracy for switch-mode power supply

  1. #1
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    High PWM frequency with 16 bit accuracy for switch-mode power supply

    Hardware: Teensy 3.6

    I am trying to build a custom switch-mode power supply that approximates a variable voltage power source with no ripple (as best as I can). To achieve this, a higher PWM frequency helps reduce the requirements of the analog components. I am aware of the diminishing returns the higher you go but I want to get the most out of this board. From the PWM https://www.pjrc.com/teensy/td_pulse.html page I found for the teensy 3.6 can produce a PWM frequency of 915.527 Hz at that resolution.

    My question would be: How can I increase this frequency?

    Own ideas:

    1: Overclock the teensy to 240mhz in order to hopefully double this frequency

    issue/question: I am not sure whether this affects the timers in the teensy

    2: Set the clockdivider value for the timers to a lower number

    issue/question: I am not even sure whether this is possible

    Edit: Not linear power supply. Variable voltage switch-mode power supply
    Last edited by Felix; 12-12-2017 at 09:22 PM.

  2. #2
    Senior Member pictographer's Avatar
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    You might consider a clock multiplier IC. Here's one example (pdf datasheet). I imagine you want high frequency switching to make it easier to filter the switching noise. You probably don't need to make adjustments nearly as fast as the output clock. Disclaimer: I have no experience with this part and I've never designed a power supply.

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    SMPS and linear source are contradictory terms where "no ripple" is your reference specification.

    There are some things that you can do to approach a low noise design, but you will not "reduce the requirements of the analog components"; you will probably increase the component count and size of the PCB space (mostly from LC components). That said, the 78xx linear regulators generally suck because of the PSSR once you go above 20 to 40kHz. If you only have hi-freq ripple, you still have ripple. And hi-freq noise causes DC offsets.

    Recently built a (discrete-component) constant-current source for LED lighting in my employer's EMC chamber. No amount of filtering the various LED drivers would meet noise floor requirements, so just built a linear CC source where Vref and gate drive opamps where 2d order filtered. The AC mains power to the CC source came through linear power transformers chosen for the cap values, where the output of the rectifier bridge went through two filters. Other than the common-mode stuff from the UUT (Long DC power wires), there was no measurable noise. FWIW, there is a T-LC, running at 24MHz that controls power to the various LED arrays, but it is located in a metal box on top of the EMC chamber.

    Microchip has some app notes on using a 16F785 as a SMPS controller.

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    Senior Member+ Theremingenieur's Avatar
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    Overclocking the CPU won’t help since the timers are clocked by the internal bus clock F_BUS which is generated by integer decision from F_CPU and may not exceed 60MHz. Thus, running the Teensy 3.6 at 120, 180, or 240MHz, you’ll always have the same bus clock of 60MHz.

    Thus, the PWM frequency when using the maximal timer resolution (16bit) is 60MHZ / 65536 = 912.527Hz. But do you really need the whole resolution? When going down to 10bit, this makes still <5mV resolution for a maximal 5V output voltage, you can already achieve a frequency of about 58.6 kHz.

    But finally, I’m not sure if these multi purpose FTMs are the best solution for a Smps. There are lots of highly specialized ICs for that out there in the wild. Combine one of these with a digipot to adjust the output voltage and control the latter from the Teensy over the SPI or I2C bus. That will give you the more reliable solution and ways less headache.

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    Member dauntless89's Avatar
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    You can overclock F_BUS by changing a config setting in (I think) one of the core libraries. I found that my project doesn't have the PWM freq/resolution requirements I thought it might, so I haven't messed with it.

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    Senior Member+ Theremingenieur's Avatar
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    Forum member FrankB has overclocked F_BUS to 96 and 120MHz, in most cases with success. But even in the best case, this doubles just the PWM frequency which is still not sufficient for controlling a SMPS with high resolution. Unfortunately, the OP has not given enough specifications (allowed ripple, ban with, noise), but let’s assume an output voltage of 5V with max 5mV ripple and noise over a 200kHz bandwidth which is pretty standard for specialized Smps controller ICs, and we are ways beyond what a Teensy can do, even when overclocked.

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    I donít think a clock multiplier like the one you linked will retain the PWM duty cycle, do you? From what it looks like that clock multiplier is designed for just 50% Duty cycle standard IO data streams.

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    Quote Originally Posted by Theremingenieur View Post
    Forum member FrankB has overclocked F_BUS to 96 and 120MHz, in most cases with success. But even in the best case, this doubles just the PWM frequency which is still not sufficient for controlling a SMPS with high resolution. Unfortunately, the OP has not given enough specifications (allowed ripple, ban with, noise), but let’s assume an output voltage of 5V with max 5mV ripple and noise over a 200kHz bandwidth which is pretty standard for specialized Smps controller ICs, and we are ways beyond what a Teensy can do, even when overclocked.
    I’m thinking of compromising on the responsiveness of the output by going with more inductors and capacitors. Do you think this approach can yield a low ripple with the downside of slow response?

  9. #9
    Senior Member+ Theremingenieur's Avatar
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    The ripple resulting from the switching frequency can be minimized either by rising the switching frequency, which explains why commercial Smps work always between 80000 and 200000Hz, or by using extremely big inductors and capacitors which is expensive and will add a delay in the load regulation which risks to worsen the stability of the output voltage. I don’t like what I tell you, but in this particular case, a specialized Smps driver IC is the way to go and not a Teensy.

  10. #10
    Senior Member PaulStoffregen's Avatar
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    If you want to try overclocking F_BUS for faster PWM, kinetis.h is the file to edit. Look for the comments in that file with info about overclocking.

    Before you build, I hope you'll consider physical pulldown (or pullup) resistors or some other circuitry to protect your power supply from doing "bad" things when Teensy reboots or is being programmed. The pins go into a high impedance state in those modes, so usually a physical resistor is needed to make sure the pin has a "safe" voltage when its not being controlled by your code.

    On the matter of ripple & noise, usually the conventional wisdom of power supply design is linear regulation. Or a switcher followed by low pass filters and a linear regulator to establish the final output. I'm not necessarily saying your switcher idea can't work, but only that the usual method for low noise looks involves a linear final output stage.

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    If your goal is a variable supply why not avoid reinventing the wheel and just use the Teensy to adjust the feedback voltage to an existing SMPS design. You can do the same thing to a linear regulator after the SMPS to further reduce noise.

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    Quote Originally Posted by Donziboy2 View Post
    If your goal is a variable supply why not avoid reinventing the wheel and just use the Teensy to adjust the feedback voltage to an existing SMPS design. You can do the same thing to a linear regulator after the SMPS to further reduce noise.
    If I do that it will use the resolution available in the switch mode power supply IC. I have not been able to find ones with 16 bit accuracy

  13. #13
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    The resolution will be based on the accuracy of your feedback, SMPS are primarily analog circuits.
    Depending on the voltage range of your supply 16bits will be tough to maintain.

    How much current do you need?

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    Thanks everyone for your input. I am going to try the strategy of using heavy analog filtering at the output. I will report back and let you know how it went early januari

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