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Thread: Cycles to LDVAL in PIT explanation (IntervalTimer)

  1. #1

    Cycles to LDVAL in PIT explanation (IntervalTimer)

    Hi everyone, I was trying to analyze the IntervalTimer function to understand the implementation and its correspondence on the data sheet.
    I cannot understand why the cycles to set on LDVALn (Timer Load VALue register) are dependent on F_BUS in IntervalTimer.h
    Here is the line 53 taken by the file at the path Programs(x86)\Arduino\hardware\teensy\avr\cores\te ensy3\IntervalTimer.h :

    Code:
    uint32_t cycles = (F_BUS / 1000000) * microseconds - 1;
    By reading at the data sheet (pag 909) it says that the period should be 20 ns = 1/50MHz:

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    Thus the number of cycles should NOT depend on the bus frequency, but I'm sure I missed something.
    Which relation exists between the formula on the data sheet and the line of code? What am I missing?

    Thanks in advance for any reply, Leo

  2. #2
    Senior Member+ Theremingenieur's Avatar
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    There is written "In the example configuration" (which seems to use a F_BUS of 50MHz).

    The PITs are definitively clocked by F_BUS (when not daisy-chained) which is 48MHz when your Teensy 3.2 runs at 96MHz and is only 36MHz when your Teensy 3.2 runs at 72MHz.

  3. #3
    Thank you @Theremingenieur... now I see! (sorry for being such a blind)

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    Pag. 902 - PIT Block Diagram

  4. #4
    Senior Member+ Theremingenieur's Avatar
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    Devo mandarti i miei occhiali?

    Shall I send you my glasses?

  5. #5
    Oui, merci beaucoup!

    (vive la France)

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