When does the PDDR definition not do what you set it to

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I wanted to set up the lower 16 bits of the D port to two 8 bit ports by the PDDR register.

PORTD_GPCLR = ( unsigned long )0XFFFF0100;
GPIOD_PDDR = ( unsigned long )0X0000FF00;

Then I expected to read and mask off the lower 8 bits

// read in unsigned long from port D
inDat = GPIOD_PDIR;

// mask bits
ret = inDat & 0XFF;

// invert data sense to positive logic
ret = ( ret ^ 0XFF );

Also the next 8 bits [8 .. 15 ] would be written to as some control flags

GPIOD_PCOR = ( 1 << 9 );
GPIOD_PSOR = ( 1 << 11 );

Here I reset one and set another this happened inside an interrupt. The problem I ran into is when I went to change the flag bits the MCU went into a eternal wait state I could only exit by reset of the MCU a Teensy 3.6

I am kinda lost why the manual says I can do this but in practice it don't do it. Am I missing something in my configuration??
 
As always showing whole code would help to debug...
Looks like you are hitting all possible 32 bits of port d... not just the 16

Also not sure where you configured the io pins to be in GPIO mode (1)
 
These two lines of code set the mode to Alt1 and the define the I/O paths, bothe require a 32 bit number or it is ignored.
The upper 16 bits indicate which of the lower bits of PORTD I am setting to Alt1. The next line sets the I/O direction
for all bits of PORTD.
 
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