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Thread: PCB layers for teensy 3.

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  1. #1

    PCB layers for teensy 3.

    Hey all - new to the teensy enviroment but looks absolutely top class and a great community.

    Have a question - how many layers are the boards for teensy? Specifically the 3.2 and 3.5 variants. I had a look on the site but all I could find was a pcb layout for the mp3 player - https://www.pjrc.com/mp3/pcb_layout_reva.html

    If there is pcb layouts hidden somewhere else for 3.2/3.5 would be very grateful if someone could point them out - but I understand if they are proprietary. I found the schematics fine but I've never worked with a chip as fast as a teensy (coming over from arduino/atmega328's which are pretty forgiving) and am curious how they are routed/if it is possible on 2 layer board without problems.

    I am interested in eventually developing a product using the chip that is constrained to 14mm width so will need to make a standalone version but I am interested see how the current one is laid out. Or just to know the no of layers.

    Many thanks

  2. #2
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    Paul may show up with the definitive answers, but I think T3.2 is 4 layer and T3.6 is 6, both pushing what is possible in that layer space. The only PCB layout in public domain is the T3.6 reference PCB floating around from the beta
    https://blog.oshpark.com/2017/04/27/...ference-board/
    Which is not the BGA version.

  3. #3
    Quote Originally Posted by GremlinWrangler View Post
    Paul may show up with the definitive answers, but I think T3.2 is 4 layer and T3.6 is 6, both pushing what is possible in that layer space. The only PCB layout in public domain is the T3.6 reference PCB floating around from the beta
    https://blog.oshpark.com/2017/04/27/...ference-board/
    Which is not the BGA version.
    Thanks - that was extremely helpful, cheers!

  4. #4
    Senior Member Epyon's Avatar
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    It is possible for the 3.2, but requires a significantly larger PCB size and careful routing to achieve optimum impedance.

    There are no layout files available for any of the official boards. If you really want to start hardware product development, you should be able to make a layout yourself .

  5. #5
    Quote Originally Posted by Epyon View Post
    It is possible for the 3.2, but requires a significantly larger PCB size and careful routing to achieve optimum impedance.

    There are no layout files available for any of the official boards. If you really want to start hardware product development, you should be able to make a layout yourself .
    Yes I find looking at things is very useful to help figuring them out. My knowledge of electronics is fairly basic but I've improved a lot in the last year and I'd love to learn more. Often I learn the hard way (e.g a couple of things learned in my last arduino project - the neccessity of keeping boost converter loops tight, the importance of reading data sheets for application/example layouts, all 10uF caps are not the same.. etc etc) - and I was curious to know more about the layout. I'm loosely aware that the higher clock speed may present more challenges and am aware I have loads to learn (4 layer routing, differential pairs, good DAC practise) - but trying to find exactly what I need to learn/identifying potential challenges is pretty tricky - and when they do come up, it is puzzling to keep breaking chips for weeks with no idea why.. Really like the sound of this forum and the helpful folks though

  6. #6
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by fishy1 View Post
    eventually developing a product using the chip that is constrained to 14mm width
    14 mm will be incredibly difficult, unless you bring out only a small number of pins. Even then, not easy!

    interested see how the current one is laid out.
    The files aren't published, but somewhere in the 3.6 beta thread I did share some images showing the layout. Maybe you can find those with a little searching?

    Or just to know the no of layers.
    3.2: 4 layers, 1 for ground plane. The 1 internal non-plane layers is mostly horizontal routing.

    3:6: 6 layers, 2 for power & ground planes. Both internal non-plane layers are mostly horizontal routing.

  7. #7
    Quote Originally Posted by PaulStoffregen View Post
    14 mm will be incredibly difficult, unless you bring out only a small number of pins. Even then, not easy!



    The files aren't published, but somewhere in the 3.6 beta thread I did share some images showing the layout. Maybe you can find those with a little searching?



    3.2: 4 layers, 1 for ground plane. The 1 internal non-plane layers is mostly horizontal routing.

    3:6: 6 layers, 2 for power & ground planes. Both internal non-plane layers are mostly horizontal routing.
    The man himself - super helpful, thanks very much.

    Only need about 15 pins out, the application is for a small musical instrument - I currently have an atmega doing the job but teensy seems like it would offer up enormous benefits which could translate to greatly improved sound quality (when I figure out I2S and how to use DAC's well etc) and the teensy system is a lot less intimidating than attempting to program something new on a new/little supported chip..

    Thanks again! Also - don't suppose you remember how many layers your audio wav shield is?

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