Teensy3.6 clock frequency

[Jacob.Schultz]

I found a mismatch in the 180 Mhz clock configuration in Tensyduino

The only way to hit a 180 Mhz clock in HS mode exactly with a 16 Mhz crystal with Kinetis own online clock tools is the following parameters:

MCG.VDIV.scale, value: '45'
MCG.PRDIV.scale, value: '2'
SIM.OUTDIV2.scale, value: '3' - gives 60 Mhz bus clock

and it looks like Teensyduino is running a 116 Mhz core and 58 Mz bus in 180 Mhz mode. The OUTDIV2 must be 3 anyway since 180/3 = 60

VDIV = 29
PRDIV = 1
OUTDIV2 = 2



is it correct assumed? I have verified that the clock frequency according to Kinetis configuration is working correct.

 

[WMXZ]

I have verified that the clock frequency according to Kinetis configuration is working correct.

How?
Show proof of wrong clock

 

[Jacob.Schultz]

Is a bus divisor that equals 2 not proof enough.
180/2 != 60 Mhz

 

[manitou]

how do your paper arguments compare with what your scope says?

look at k66 ref pg 262 (SIM_CLKDIV1) SIM_CLKDIV1_OUTDIV2(2) ( 2 means divisor of 3) RTFM

from mk20dx128.c

#elif F_CPU == 180000000
    // config divisors: 180 MHz core, 60 MHz bus, 25.7 MHz flash, USB = IRC48M
    #if F_BUS == 60000000
    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(6);

...

https://www.pjrc.com/teensy/datasheets.html

 

[Jacob.Schultz]

Sorry, your right nothing is wrong, i was cheatet by some macro translations Teensyduino code is using the raw register values not human readable.

VDIV 11101 45