Tri-sync pulse generator

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plemon

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Hi,

I am attempting to create a tri-sync pulse generator so I can sync two of my cameras together and am wondering if the Teensy can create a pulse with the following specs:

A negative-going pulse of 300 mV lasting 40 sample clocks followed by a positive-going pulse of 300 mV lasting 40 sample clocks. The allowed rise/fall time for each of the transitions is 4 sample clocks. This is with a clock rate of 74.25 MHz

Is this a PWM task? Am I right in assuming if the clock rate needs to be 74.25Mhaz that the Teensy must run at this speed? Can the 3.2 be run at 74.25 instead of 72? Or am I on the wrong track here?

Also, is there a recommended device for evaluating the output so I can check the signal?

Phil
 
I would be interested also, Planning to use Teensy 4.0, any suggestions how to handle the timing.?


Here is about try-level synch


https://jwsoundgroup.net/index.php?...GDS6xHgbuNJ5VznSPhe0js7yq2TReLz6zSeYQy30EdLJE


plemon said:
Hi,

I am attempting to create a tri-sync pulse generator so I can sync two of my cameras together and am wondering if the Teensy can create a pulse with the following specs:

A negative-going pulse of 300 mV lasting 40 sample clocks followed by a positive-going pulse of 300 mV lasting 40 sample clocks. The allowed rise/fall time for each of the transitions is 4 sample clocks. This is with a clock rate of 74.25 MHz

Is this a PWM task? Am I right in assuming if the clock rate needs to be 74.25Mhaz that the Teensy must run at this speed? Can the 3.2 be run at 74.25 instead of 72? Or am I on the wrong track here?

Also, is there a recommended device for evaluating the output so I can check the signal?

Phil
Click to expand...
 
Do you need to generate the sample clock also, or just the -0.3V/+0.3V sync pulses/pulse pairs?

If we look at just the sync pulse (pair) itself, starting at 0V (idle):
  • The output drops to -0.300 V ± 0.006 V for 538.72 ns (reaching the level within 54 ns)
  • The output rises to +0.300 V ± 0.006 V for 538.72 ns (reaching the level within 54 ns)
  • The output drops to 0V (within 54 ns)

If we consider a Teensy 4.0 running at 600 MHz, the low and high levels take 323 clock cycles, including the max. 32 cycle transition times. So, the speed should not be a problem.
Slew-rate wise, we need 0.6V in 54ns, which is about 11.1 V/µs; I'd prefer some leeway, so say 20 V/µs.

Implementation-wise, I think using a timer and a DMA would work just fine: the timer would trigger every 538.72 ns (323 clock cycles = 538.333 ns), and the DMA would transfer 3 bytes to an appropriate GPIO register: first one would set one pin pulling the output to -0.3V, the second one would clear that pin and set another pin pulling the output to +0.3V, and the third one would clear both. If the sync pulse repeats at some interval, the DMA can either be extended in 538.333ns units (requiring about 1858 bytes per millisecond), or triggered by another timer (perhaps chained to another DMA). Good choices for these pins would be 6 and 9, B0_10 and B0_11, respectively, in the schematic; pins 10 and 11, respectively, of GPIO7; the DMA directed to second byte of GPIO7_DR_TOGGLE bits 2 and 3 (bit 2 being set changing the state of pin 6, and bit 3 being set changing the state of pin 9, between 0V and 3.3V).

The "hard part" is to generate those exact voltage levels. Teensies normally only support positive signaling, so you'll need some kind of support circuitry. There is very little leeway in the voltage levels; both levels must be correct to within 2% (±6 mV of ±300 mV); plus the slew rate across zero must be above 11 V/µs to fulfill the timing requirements.

Unfortunately, I'm just a hobbyist myself, and not sure at all what kind of circuit would work here. If this were my project, I'd head over to EEVblog forums, Beginner section, and ask what kind of circuit a beginner could buils to generate -0.300 V ± 0.006 V and +0.300 V ± 0.006 V pulses (referenced to 0V/GND) with 20 V/µs or higher slew rate.
 
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