attachInterrupt(2, spi0_isr, FALLING);
After further tests, the spi0_isr is way more faster at data capture than the pin interrupt
16 will have to move forward in the direction of shared variable usage protection that im currently still researching, the errors only occur when both the isr and main access the same queue, because it can be replicated with the slave queue, itll help me test different things after i do a little research
btw, to test the interrupt you didnt need all that code
justin setup(), and comment out the nvic enable, doneCode:attachInterrupt(2, spi0_isr, FALLING);
slave.beginSlave( SPI_SLV_CS );
25256.00, #, #, #, #, #, #, #, #, #, #, #,187788,3
Bad LASTVAL TEST INCREMENT <<<<<<<<<<<<<<<<<<<< DIFF OF> -12.00
25280.00,25281.00,25282.00,25283.00,25284.00,25285.00,25286.00,25287.00,25288.00,25289.00,25290.00,25291.00,187789,4
25292.00, #, #, #, #, #, #, #, #, #, #, #,187790,4
4232.00, #, #, #, #, #, #, #, #, #, #, #,284338,5
Bad LASTVAL TEST INCREMENT <<<<<<<<<<<<<<<<<<<< DIFF OF> -12.00
4256.00,4257.00,4258.00,4259.00,4260.00,4261.00,4262.00,4263.00,4264.00,4265.00,4266.00,4267.00,284339,6
4268.00, #, #, #, #, #, #, #, #, #, #, #,284340,6
SLAVE::
43368.00, #, #, #, #, #, #, #, #, #, #, #,1067552,1
MASTER::
F&F (OT=1)micros() _time==49
NVIC_SET_PRIORITY(IRQ_PORTD, 0);
attachInterrupt( addr, CS_isr, FALLING );
your saying the v16 has errors using spi0 isr? with nvic set to 1 ?
This prior post saw errors gone in V16 - about the same rate as with CS driving the SPI - but one interrupt per transfer instead of 100.
spi0isr #26 csisr #52
#define Serial4 Serial1
#define Serial5 Serial1
#define Serial6 Serial1