Project: SPI_MSTransfer

defragster · Mar 10, 2018

Yeah - abandon the CS code - once I counted the interrupts 2 CS fpr 1 spoi0 it was not only solving the wrong problem - but not in a better way.

Both my MST systems running since noted - NO ERRORS.

tonton81 · Mar 10, 2018

oh i understood it worked better than the spi interrupt

defragster · Mar 10, 2018

No - that misconception was corrected in prior posts - in one case re-reading that was V16 used in earlier posts to good end and then when isr() hit rate was counted.

Did you figure out a way handle the isr queue separate from the user's Master push queue?

Need to add the FULL_SPEW but instrumented F&F messages as well as the DEBUGHACK version as distinct F&F messages for the Master to send and the Slave to handle distinct from the True TViewer messages.

Tony: If you want to make an MST V_0.1.0 version with the working F&F code and the #ifdef{serial} we can make that the current basis for the other thread. That thread doesn't have urgent need for Slave Push.

tonton81 · Mar 10, 2018

ok

View attachment SPI_MSTransfer 0_1_0.zip

added ifdefs for serial

tonton81 · Mar 10, 2018

this must be some fluke thing but...
im letting this run at 50ms slave -> master transfers, with a little details...

slave transfer16 method mod:

Code:

    __disable_irq();
    teensy_stm_queue.push_back(_vector);
    //      if ( teensy_stm_queue.size() > 14 ) teensy_stm_queue.pop_front();
    spi0_isr();
    __enable_irq();
    NVIC_SET_PRIORITY(IRQ_SPI0, 0); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ

reason why something is fishy, but working?... as a trick first i disable the interrupts
immediately after queuing a slave's payload, i call the spi0_isr directly, in case it missed a "fire" while disabled (this aparently stopped most errors!?) (it will exit if nothing to do)
next i reenabled interrupts
but the thing is, eventually it will crash again, so i tested with resetting the SPI NVIC priority
what the heck!? its still going?!?
does disabling/reenabling interrupts reset the IRQ's???????????????????????????

Code:

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Code:

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EDIT, just got ONE error but still going

tonton81 · Mar 10, 2018

Im thinking the error could be at the master->slave end as well when it's getting dequeued from loop while isr refires, so i put this in the slave events:

Code:

    __disable_irq();
      auto _deque = move(teensy_handler_queue.front());
      teensy_handler_queue.pop_front();
    spi0_isr();
    __enable_irq();
    NVIC_SET_PRIORITY(IRQ_SPI0, 0); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ

now lets wait and see

tonton81 · Mar 10, 2018

touching the master -> slave one caused lockups after a while, so i reverted those changes and trying something else for slave->master:

Code:

    __disable_irq();
    teensy_stm_queue.push_back(_vector);
    if ( !(GPIOD_PDIR & 0x01) ) spi0_isr();
    __enable_irq();
    NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ

now it checks for pin low state before firing spi0_isr and then enables interrupts, letting it run

note: this is with these in master loop() without millis delays, so i flood as much as possible, but it's keeping up at 0 errors. T3.5S120, T3.6M180,30mhz

Code:

teensy_gpio.digitalWrite(13, !teensy_gpio.digitalRead(13));
teensy_gpio.events();

edit1: 1 error after 5 minutes

tonton81 · Mar 10, 2018

this one runs the longest without errors

Code:

uint16_t SPI_MSTransfer::transfer16(uint16_t *buffer, uint16_t length, uint16_t packetID, bool fire_and_forget) {
  if ( _slave_access ) {
    uint16_t data[6 + length], checksum = 0, data_pos = 0;
    data[data_pos] = 0xAA55; checksum ^= data[data_pos]; data_pos++; // HEADER
    data[data_pos] = sizeof(data) / 2; checksum ^= data[data_pos]; data_pos++; // DATA SIZE
    data[data_pos] = 0x0000; checksum ^= data[data_pos]; data_pos++; // SUB SWITCH STATEMENT
    data[data_pos] = length; checksum ^= data[data_pos]; data_pos++;
    data[data_pos] = packetID; checksum ^= data[data_pos]; data_pos++;
    for ( uint16_t i = 0; i < length; i++ ) { data[data_pos] = buffer[i]; checksum ^= data[data_pos]; data_pos++; }
    data[data_pos] = checksum;
    std::vector<uint16_t> _vector(data, data + data[1]);
    __disable_irq();
    teensy_stm_queue.push_back(_vector);
    if ( !(GPIOD_PDIR & 0x01) ) {
      spi0_isr();
      __enable_irq(); 
      NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
      NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
    }
    else {
      __enable_irq(); 
      NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
      NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
    }
    return packetID;
  }

you'll have to patch another section in the spi0_isr if we call it manually:

Code:

    /* BEGIN PROCESSING */


    while ( 1 ) { // wait here until MASTER confirms ACK receipt

to:

Code:

    /* BEGIN PROCESSING */


    while ( !(GPIOD_PDIR & 0x01) ) { // wait here until MASTER confirms ACK receipt

doing this with above T16 patch and more than 10 minutes no errors

heres my patched files for testing

View attachment testing.zip

tonton81 · Mar 10, 2018

yup, after awhile it does end up locking, but at least its more proof its a queue pop/push issue

aparently the STL queues use malloc, which is never safe in an isr according to articles online

defragster · Mar 10, 2018

tonton81 said:
... aparently the STL queues use malloc, which is never safe in an isr according to articles online

And according to suggestions in my prior post ....

tonton81 · Mar 10, 2018

any ideas for exporting the buffer contents than?

im wondering how fast those vector swaps are
perhaps we add a secondary queue just for the ->master transfer, and if the slave detects during loop() time that the queue is empty, it does a swap on the queue which actually doesnt move/copy, it just swaps the pointers of the arrays so the other end would be full and the local one empty

defragster · Mar 10, 2018

Static Buffers with Active/Used flag tracking in some fashion.

The Microcontroller world is like my old job . . . raw "C" only.

tonton81 · Mar 10, 2018

cant do static with dynamic sized arrays, and without FIFO fashion

tonton81 · Mar 10, 2018

you mean a static array to store the buffer, and after ISR, to queue it? how can you get it queued fast enough before next loop iteration before ISR fires again to overwrite it's contents? lots of hoop testing here

defragster · Mar 10, 2018

"Can't" sounds sort of negative - when anything is possible

... It is a paired system - set constraints and limits as appropriate. Max message size - multi part if needed.

tonton81 · Mar 10, 2018

now im trying with volatile bool _stm_queue_busy = 0;

1) for the transfer16 on slave i set _stm_queue_busy to 1.
2) in the ISR, if the value is 0 and the queue exists, THEN read the front of the queue, but DONT DEQUE (commented out)
3) in events, if _stm_queue_busy is set, POP the front queue and THEN unset _stm_queue_busy.

ONLY events can UNSET the bool
ISR & T16 can ONLY SET it
ISR ignores transfers if set
so far its working! (the POP is done from EVENTS, NOT ISR)

tonton81 · Mar 10, 2018

im using 2 flags now actually
one for events() to DEQUE with ISR flag, and a flag for T16, telling ISR to not transfer any data while it's queing up another queue

im slamming 50ms slave loops now for transfers -> master

View attachment booltest_2.zip

this needs testing but i think it works!?

unless loop() wipes out the flag, all further ISR transfers wont happen until loop wipes flag AFTER POPPING the queue (that was already transfered)

this does NOT stop the slave from queuing up more data!

test this pls!

so for the QUEUE system for the SLAVE -> MASTER now ONLY THE MAIN LOOP HAS ACCESS TO POP&PUSH (NOT ISR)

tonton81 · Mar 10, 2018

reference modification points for slave -> master:

::transfer16 method

Code:

uint16_t SPI_MSTransfer::transfer16(uint16_t *buffer, uint16_t length, uint16_t packetID, bool fire_and_forget) {
  if ( _slave_access ) {
    [B][COLOR="#FF0000"]_stm_queue_busy = 1;[/COLOR][/B]
    uint16_t data[6 + length], checksum = 0, data_pos = 0;
    data[data_pos] = 0xAA55; checksum ^= data[data_pos]; data_pos++; // HEADER
    data[data_pos] = sizeof(data) / 2; checksum ^= data[data_pos]; data_pos++; // DATA SIZE
    data[data_pos] = 0x0000; checksum ^= data[data_pos]; data_pos++; // SUB SWITCH STATEMENT
    data[data_pos] = length; checksum ^= data[data_pos]; data_pos++;
    data[data_pos] = packetID; checksum ^= data[data_pos]; data_pos++;
    for ( uint16_t i = 0; i < length; i++ ) { data[data_pos] = buffer[i]; checksum ^= data[data_pos]; data_pos++; }
    data[data_pos] = checksum;
    std::vector<uint16_t> _vector(data, data + data[1]);
    teensy_stm_queue.push_back(_vector);
  [B][COLOR="#FF0000"]  _stm_queue_busy = 0;[/COLOR][/B]
    return packetID;
  }

ISR:

Code:

                if ( [B][COLOR="#FF0000"]!_stm_queue_delete && !_stm_queue_busy &&[/COLOR][/B] !_slave_pointer->SPI_MSTransfer::teensy_stm_queue.empty() ) { // IF QUEUES EXIST, ONE WILL BE DEQUEUED TO MASTER
                  [B][COLOR="#FF0000"]_stm_queue_delete = 1;[/COLOR][/B]
                   [B][COLOR="#FF0000"]// 2 lines deleted (queue move & deque)[/COLOR][/B]
                  uint16_t checksum = 0, _deque_pos = 0;
                  while ( !(GPIOD_PDIR & 0x01) ) {
                    if ( SPI0_SR & 0xF0 ) {
                      SPI0_PUSHR_SLAVE = [B][COLOR="#FF0000"]_slave_pointer->SPI_MSTransfer::teensy_stm_queue.front()[/COLOR][/B][ ( _deque_pos > [B][COLOR="#FF0000"]_slave_pointer->SPI_MSTransfer::teensy_stm_queue.front()[/COLOR][/B][1] ) ? _deque_pos = 0 : _deque_pos++];
                      if ( SPI0_POPR == 0xD0D0 ) { SPI0_SR |= SPI_SR_RFDF; return; }
                    }
                  }
                  SPI0_SR |= SPI_SR_RFDF; return;
                }

events()

Code:

  if ( _slave_access ) {
[B][COLOR="#FF0000"]    if ( _stm_queue_delete ) {
      _slave_pointer->SPI_MSTransfer::teensy_stm_queue.pop_front();
      _stm_queue_delete = 0;
    }[/COLOR][/B]

as i typed all this, its still pounding at 50ms rates and 0 errors!

defragster · Mar 10, 2018

Cool.

Maybe go ahead and release an complete V_0.2.1? - I don't see the define of _stm_queue_bus or _stm_queue_delete. I'll try it out - but don't want to get stuck on my poor editing. You can edit the base Master and Slave ino for new Examples if you want for testing - or add a "StoM" version? I'm going to port the existing examples to "TV_" for TViewer usage on 'other' thread to assure those are clean and working and easy to track.

tonton81 · Mar 10, 2018

here it is!

View attachment SPI_MSTransfer 0_1_1.zip

mjs513 · Mar 10, 2018

Can I still use the examples I used earlier for testing 2-way or do you have different ones?

tonton81 · Mar 10, 2018

same examples, just now i replaced volatile with std::atomic bool instead, because "a volatile variable does not guarentee enforcing any memory barriers nor any cache mechanism"

been reading up online and std::atomic seems to be well defined and better to use than volatile

Code:

std::atomic<bool>_stm_queue_busy;
std::atomic<bool>_stm_queue_delete;

View attachment SPI_MSTransfer 0_1_2.zip

Changed volatiles to c++ atomics

mjs513 · Mar 10, 2018

From what I understand with atomic variables you need to use store and load with them? If you run into trouble with them you may want to check out http://en.cppreference.com/w/cpp/atomic/atomic_flag.

EDIT> This is beginning to sound like Dune - using Atomics

tonton81 · Mar 10, 2018

store and load are the same as operator =, according to online searching

mjs513 · Mar 10, 2018

Usually. I ran into a problem with going back and forth between atomic's and non-atomic's. For instance I couldn't get an atomic to print with serial.print so I had to assign it to a non-atomic. Forgot the exact syntax I was using but that one I remember. Figured I would just mention it, just in case

EDIT> Running it now. Still won't do 120/120 but 168/120 works. So far so go. Have 1 OT but that was on start up.
EDIT1> Test conditions - master loop at 20ms and slave loop for transmit at 20ms.

Project: SPI_MSTransfer

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