Project: SPI_MSTransfer

[mjs513]

Don't know if this is related or not to what tonton81 was looking at: https://forum.pjrc.com/threads/50442-SPI-clock-polarity-setup-not-long-enough?highlight=spi+polarity

 

[defragster]

Don't know if this is related or not to what tonton81 was looking at: https://forum.pjrc.com/threads/50442-SPI-clock-polarity-setup-not-long-enough?highlight=spi+polarity

That's the errata issue thread I was referring to. That only affects when multiple devices are on SPI bus with alternate polarity setup between access.

Might be interesting to do a test with alternate 'mode' settings ?

 

[tonton81]

OK I GOT IT!!!! i got both running at 1mhz!!!

 

[tonton81]

I GOT 1 KHZ WORKING!!!

F&F (OT=0) OT_CALC==3000000  micros() _time==24784
F&F (OT=0) OT_CALC==3000000  micros() _time==24784
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24784
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24783
F&F (OT=0) OT_CALC==3000000  micros() _time==24784

 

[mjs513]

You going to keep us in suspense or what

EDIT: Tim got it.

 

[tonton81]

Yes mike!

Short answer!

Spi slave register configuration ordering is important! THAT OR the 3.2 isnt capable of a single ninstruction set!!

 

[mjs513]

How the heck did you find that one?

 

[tonton81]

Trial and error!?!?! AND A POWER NAP!

I knew something was wrong when the BUS WAS UNAFFECTED by the T3.2 slave crashing when the T3.5 continued operation!
So I went to poke around the registers!

 

[tonton81]

Can you test and let me know your 3.2 functionality at all speeds????????????????

[ATTACH]13641._xfImport[/ATTACH]

 

[mjs513]

Amazing what a power nap can do for you. Glad you found the root cause of the all the issues with the 3.2

Will do and let you know shortly

 

[tonton81]

oh just so you know, 3.2 still cant do 30 but less is ok

 

[tonton81]

even 1Hz is working lol

EDIT: events(0) is working with 400uS f&f’s!
but thats too much overhead, leave events() blank, it defaults to 500uS

 

[mjs513]

Ok did a whole bunch of testing, master at 168Mhz and slave at 120Mhz:

• Max is 26Mhz but you get a bunch of OTs so for practical purposes 24Mhz should be the max
• Tested down to 500hz and worked even at that speed.
• Can't even remember all the speeds I tested at but I remember 4Mhz, 14Mhz 10Mhz.

With Master at 120Mhz and slave at 120Mhz still worked at 24MHz

With Master at 120Mhz and slave at 72Mhz and bus at 24Mhz worked but now well, get a lot of OTs on the master side and bad lastvals on the slave side and the transfer is choppy. Probably get better results adjust events/timer.

By the way all tests done with 1ms loops and 0us events.

 

[tonton81]

awesome! Can I dismantle my dual slave setup and poke around the LC?

 

[mjs513]

Yes you have my permission Guess I will have to solder up the LC just so I can give you more problems to solve.

 

[tonton81]

LC not supported yet, so no rush

 

[mjs513]

I know - but I some other soldering to do anyway so I might as well do that at the same time I usually solder in batches...

 

[mjs513]

3.5/3.5 Not working

Eh Tony. As a test I went and loaded the master and slave sketches on the two 3.5's.

Unfortunately it is not running - getting F&F's on the master but nothing on the slave. Same sketches used on the 3.5/3.2 combo except I left SPI at 30Mhz.

Do you think the spi order that you had previously is good for the 3.5/3.6 while the order for 3.2 is different?

 

[tonton81]

If it is... I can always add if/def's to make it automatic switchable

can you try to copy the old ::begin() over to test?

 

[tonton81]

Keep the SAME library, just change in the CPP, let me know if that works:

Change this:

    SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock

    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
    SPI0_MCR = 0x00000000;
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;

    SPI0_CTAR0_SLAVE = 0;
    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
    SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15);
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;

    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
    SPI0_CTAR0_SLAVE = SPI0_CTAR0_SLAVE & ~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25;
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;

    SPI0_RSER = 0x00020000;

    CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
    CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN2_CONFIG =  PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
    NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ

To this:

    SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock
    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS; // stop
    SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15) & SPI0_CTAR0_SLAVE & (~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25);
    SPI0_RSER = 0x00020000;
    CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
    CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN2_CONFIG =  PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS; // start
    NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ

Then upload to your slave

 

[tonton81]

I don't think we'll be able to do LC... the LC requires writes to 2 addresses, and without re-writing all the switches in the ISR to compensate for 2 writes, we can't do much
The register expects 8bit writes only, and the POPR & PUSHR_SLAVE (kinetisK) is a SPI0_DL (lower byte register) and SPI0_DH (upper register) for the data, for in and out its the same register.

This would require re-writing a complex sphagetti code with ifdef's everywhere....

Mike, did you get the section of code changed for result?

 

[tonton81]

Also remember to use events(500) (if you used old sketches... ) they might be set lower...

 

[defragster]

I don't think we'll be able to do LC... the LC requires writes to 2 addresses, and without re-writing all the switches in the ISR to compensate for 2 writes, we can't do much
The register expects 8bit writes only, and the POPR & PUSHR_SLAVE (kinetisK) is a SPI0_DL (lower byte register) and SPI0_DH (upper register) for the data, for in and out its the same register.

This would require re-writing a complex sphagetti code with ifdef's everywhere....

LC with less RAM and speed would run at slower speeds and the RAM hit would be higher % - so maybe not worth too much trouble?

It would work for Master as you use standard SPI# routines right?

It would "just" take a single #ifdef ... alternate spi0_isr() for use on T_LC?

Just like it would take an alternate spi#_isr() to support SPI1 or SPI2 _isr() for T_3.5 and T_3.6?

 

[tonton81]

I cant seem to get it above 24mhz either, even with the old SPI registers. The working one should be recommended though because "it works" for both, the 30mhz issue is from something else....

 

[tonton81]

Yeah but we need to push 2 8bit registers SPI0_DL && SPI0_DH, and read them like the POPR, it's a 2 way register, but thats alot of ifdefs and code rewriting to adapt!
it's not as simple as a redefine...