mjs513
Senior Member+
Don't know if this is related or not to what tonton81 was looking at: https://forum.pjrc.com/threads/50442-SPI-clock-polarity-setup-not-long-enough?highlight=spi+polarity
Don't know if this is related or not to what tonton81 was looking at: https://forum.pjrc.com/threads/50442-SPI-clock-polarity-setup-not-long-enough?highlight=spi+polarity
F&F (OT=0) OT_CALC==3000000 micros() _time==24784
F&F (OT=0) OT_CALC==3000000 micros() _time==24784
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24784
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24783
F&F (OT=0) OT_CALC==3000000 micros() _time==24784
SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
SPI0_MCR = 0x00000000;
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;
SPI0_CTAR0_SLAVE = 0;
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15);
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
SPI0_CTAR0_SLAVE = SPI0_CTAR0_SLAVE & ~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25;
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;
SPI0_RSER = 0x00020000;
CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
CORE_PIN2_CONFIG = PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS; // stop
SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15) & SPI0_CTAR0_SLAVE & (~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25);
SPI0_RSER = 0x00020000;
CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
CORE_PIN2_CONFIG = PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS; // start
NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
I don't think we'll be able to do LC... the LC requires writes to 2 addresses, and without re-writing all the switches in the ISR to compensate for 2 writes, we can't do much
The register expects 8bit writes only, and the POPR & PUSHR_SLAVE (kinetisK) is a SPI0_DL (lower byte register) and SPI0_DH (upper register) for the data, for in and out its the same register.
This would require re-writing a complex sphagetti code with ifdef's everywhere....