Project: SPI_MSTransfer

Tony, tried that already but that version is causing me problems as well. Remember I am also setting sSer3 to serial3 to pass arguments back to the master. But based on your examples not using sSer3 events in the master. Just wanted to be complete :)
 
ok i just wanted to make sure if older events worked on slave end while the latest thread test version was commented out on master, its puzzling but if i have to follow the steps in events()

slave is getting the f&fs fine, its the reception to master thats fubard
 
Not a problem. Don't mind testing. Just to let you that I got uNav working with the old library working again - it was something with the new calibration methodology that Don put together.

Test1: no events in master - no issues with F&Fs
Test2: with aHRS.events() in master - works fine with F&Fs

Did you try using something like codeCompare to see where the changes were that you made between versions?
 
ok Mike, not to worry, it's a mix of problem... It's probably not events, but I have to fix the ISR switch statements first...
The reason is theres a ISR flag & return in the wrong spot that I found and now im getting the slave data in master fine with events in loop, so I'm gonna start going line by line after a autotext IDE format to verify the switches
the reason why the F&F's worked was because they never entered that switch statement...

theres alot of flag clears and returns, it needs to be cleaned up anyways, compared or not, not sure if itll get done today tho cuz i goto work in a few hours, but at least i found the problem
 
Tony. Don't worry about it, no rush. This is what testing is suppose to do - identify problem areas that need to be tweaked. Part of the process. SPI_MSTransfer got more and more complicated as you started adding more and more options - so its to be expected. Take your time.

Get some coffee and rest before you have to go to work. I am retired so I don't have that problem but I have to get things done around the house when the weather cooperates :)

I'll go play with uNav now and be quite.
 
Last night I was so tired looking through the code... then when I woke up, I didn't even know how I walked to bed, I don't remember... I was just in bed lol...
 
Hey Mike, I had a brilliant idea...

I was thinking of doing like I did to the lambda function, where the methods KNOW it's active or not...

Just think for a moment, what if we create an additional CBA with 2 entry...

Here's the idea...

When the ISR fires, it will know when the slave is DEQUEING processes from previous F&F (which is not complete yet...). This is great also for people sharing data between ISR & loop...
Tim, you might like this....

So rather than accessing the same QUEUE (at same time), the slave will have 2 QUEUE for incomming. ONLY one will be chosen to be written to, depending which is being accessed, the other will be the candidate.
The slave will dequeue from both sides, but incomming master data will write to the one thats "not busy"

What do you think? :)
or rather than 2 QUEUE, why not split the queues, 16 queues == 8, 8

EDIT: the ISR will choose which to write to, ex: if events() on slave is dequeueing CBA1, CBA2 will be the target of the F&F, and if slave is dequeueing CBA2, CBA1 will be target for F&F
The slave will dequeue both sides, not all at once, but taking turns, example
everytime events() will be called, it dequeues CBA1, and next events() CBA2, etc, this can be a simple switch via a bool... this balance will prevent incomming overflows from occuring on both sides i would think

EDIT2:
something like this:
Code:
      _slave_dequeue_active = 1;
      mtsca.pop_front(array, sizeof(array) / 2 );
      _slave_dequeue_active = 0;

based on that volatile variable, the ISR would target the 2ndary buffer for an F&F incomming packet...

BTW, I could do the same for when the MASTER collects... If the SLAVE is writing to the OUTPUT buffer and is not complete, the ISR will be told to tell the master's events() that theres no queues so it wont dequeue, and next round trip to events() would pull it if it's not busy writing back to master :)
 
Last edited:
Here's the example I did when I wrote the lambda handler for I2C:

Code:
                  [COLOR="#FF0000"]_wire_callback_active = 1;[/COLOR]
                  _wire_callback_readpos = 0;
                  mtsca.push_front(buf, buf[1]);
                  _wire_onReceivefunc(buf[4], info);
                  mtsca.pop_front();
                  [COLOR="#FF0000"]_wire_callback_active = 0;[/COLOR]

the methods used by wire, instead of pulling the slave data from slave, which was already sent to a buffer, it queues the buffer and lets the functions know to pull from the CBA instead of requesting data from slave
 
That seems good and useful tonton81 if the 'sketch' callback takes ownership _active=1 before the isr() fires it will push isr() to the second CA, if not then the isr() will get in and update first CA and leave before it causes trouble for the callback code.

I haven't looked at CA's enough to understand the indexing to a specific CA - or if one is 'active' by default - not always the first CA[0]?
 
Question, I'm guessing BOOLs are not atomic?

I seen Paul mention that uint8_t and other data needs multiple calls whereas native 32 writes are done in a single instruction?

I setup the master to ONLY pull slave data when the slave was NOT writing it, and even still intermittantly missed entries... I was like, what the heck?
So I remembered the post about the 32 bit write as a single instruction (if i remember right) and use that to set 0 or 1....

Now it's working perfect!?????

Should we stay away from bools in ISR and just use uint32_t instead?? 32bit writes are working and bool is causing queue loss intermittantly!

im not getting any slave to master queue lost at uint32_t volatile!!
 
Tim, this bool was holding me back wondering why half the time the slave was dequeueing nothing even though it said one queue, but the master never received it, in 1 sec intervals.

ALL I DID WAS CHANGE BOOL --> UINT32_T
now i get data EVERY SECOND!!

I think people should know when using the ISRs its a good idea to use native writes! because bool doesnt work in this case unless you want to fork over more code to make the bool atomic!

EDIT, gonna try uint16_t now... to see what it does
RESULT: UINT16_T WORKS AS WELL
 
OK: Heres a log:
VOLATILE BOOL:
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UINT16_T/UINT32_T
Code:
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See!!?!!?? I switched bool to check it AGAIN and it always fails!

EDIT, UINT8_T HAS SAME SYMPTOM AS BOOL! To stop the crazyness!?!?! I put it at uint16_t as a sanity check AGAIN, and its WORKING! :eek:
 
Tim, I've implemented the slave sending to master protection while writing, its working great now with the volatile uint16_t (even though im only using 0 and 1 value!)

Should we do the CBA split, where half is assigned to 1 side, and half to the other?

/2 still results in power of 2....

OR

OPTION2:
We can add a 2 entry CBA, slave's priority check is that slot for dequeue, and if nothing, it starts on the 2nd bigger one, this will be easier to write in code...
 
Without some 'atomic' overhead - best to assume nothing is really atomic, but write of constant int32_t would be closest for a simple write in one instruction, but if testing then writing or reading setting/changing, writing the isr() could fire in there anywhere.

Not looked at what is in the atomic command path - but there is such a thing with whatever overhead that brings.
 
Well according to the console, all the data is comming in with uint16_t, so I can assure you we're safer now than we were with bool at the moment! :)

We can always "update" the variables later on to std::atomic later on or whatever, lucky for us, theyre centralized :)
 
OH MY!! Tim, I blasted the slave to write 0ms loops and ran ONLY events(0) in master loop, it was scrolling crazy with all data intact!!! i had to close the console it was flooding with the payload! :)
 
Cool - seems clean and fast and robust. Will be interesting when the loop() code is trying to do something productive or useful with that data or for creating the data to send. That would test the timing of the flow a bit more and also make sure the loop() can get work done.
 
Just swapped out the uint16_t for atomic bool, library seems to work with it...

Code:
std::atomic<bool> SPI_MSTransfer::_slave_queue_active = ATOMIC_FLAG_INIT;
std::atomic<bool> SPI_MSTransfer::_slave_dequeue_active = ATOMIC_FLAG_INIT;

I'm out of time, gotta beat traffic, most likely I'll continue on tomorrow with the code as progress of *improvement*, due to the bug, is progressing.. :)

Hey, if it wasn't for the QUEUE system and I2C/SPI, we wouldnt have found a better way! :)

I'll be on chat tho via phone web app here on the forums,
Also would like to work on the smart queue redirect feature for data handling, im just wondering how fast the ISR is if its able to override one queue too quickly before it gets to the other if the slave was still "busy" with it hmmm
That would be an awkward surprise
 
Geez - just got back on the computer - wow missed a lot again. Well guess you found out bools are not atomic :) Should have checked sooner but nothing came through on the emails. BTW: Didn't we talk about atomic bools before or is this just deja vu.
 
either way, this is looking good, ill spend some quality time on it :)
if you got suggestions for tackling dual buffer system rather than a single only problem is can the isr fire 2x or more faster than the loop? im worried about a smaller buffer backup overflowing if the SPI ISR fires more than 2-3 times if we have a 2 FIFO CBA queue
the transaction of the CB push from loop is between

atomic bool 1
write CBA
atomic bool 0

wonder if the ISR will give enough time for loop to release since loop will prioritize the backup buffer before main
 
... always room for adjustment - take first from whichever is more filled? isr() can go secondary if first is [ in use - or - full ].
 
well not really more filled, the secondary one was just if the first was “in-transition”

otherwise i see no benefit in filling ones less full, especially if ordering is required, wait, thats also a doorstopper right there, we’ll lose ordering if we go double queue route
 
Slave's been pumping out since I left today, its still rolling along! :D didnt crash yet! I fixed Don's issue so my deed for the night is done, tomorrow I'll see what I can do with MST...
 
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