It's not the monitor the issue, the monitor works, it shows me its running a slightly older library i flashed before the LC patch
It just taking the upload in one ear, and out the other...
EDIT, since this mess got me started, I went ahead to update to beta4 from beta3. It's working now lol
EDIT, ok confirmed 300khz works on 3.6 -> LC, 3.5 pauses, bringing 3.5 down to 100KHz gets rid of the pauses...
EDIT
T3.5 120mhz 100khz OK, 4mhz f&F
T3.5 168MHz 200khz OK, 4mhz f&F
T3.5 120mhz 200khz OK, 4mhz f&F
But your right, 200 would be max for a T3.5 to control a TLC, except the F&F's. Don't forget the DSPI interface on the kinetisL is a different animal. I can only conclude that the LC has issues with continuous traffic, especially with a single register harvesting input and output data, I would imagine the LC needs time to switch the register from in to out or back and requires more time to do so, one user reported on another forum that a similar chip needed 4x the delay just to work properly..., we're not using delays (much) except between SPI transfers, so we're lucky to get this far, i guess