Project: SPI_MSTransfer

It this with T_3.2 as Master? At what F_CPU? For F_CPU at 96 then F_BUS is 48 and it won't work over 24 - per the spec. It might hit SPI of 30 MHz with OC to F_CPU==120 and F_BUS==60?
 
No, I reattached the T3.5, however it doesnt seem to work at 30 anymore, 24 is okay, maybe its the wires.... ? heh
definately not the SPI0 registers this time
 
Hi Tony. Just got back online - I'll give the code changes a shot and see what happens :)

Ok - just made the change and uploaded to the slave - and I made sure events was at 500. All worked fine with change you recommended. So I guess a ifdef has to be added.

Still reading the posts on the LC.
 
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Yeah but we need to push 2 8bit registers SPI0_DL && SPI0_DH, and read them like the POPR, it's a 2 way register, but thats alot of ifdefs and code rewriting to adapt!
it's not as simple as a redefine...

Is all the SPI R/W in the _isr() ? If so an alternate LC::spi0_isr() would need everything rewritten. But just one #ifdef :)
 
Im getting 4790Hz now F&F overload1 with the working SPI0 registers using T3.6 master and T3.5 slave, stock cpus 30mhz spi bus, using default events() (500uS) and 200uS timer F&F's
 
5312Hz at 180uS F&F overload1 loops! Tim, im sure you can push 6K if 20uS makes a difference on a T3.5 lol

5010 at 190uS F&F loops()
 
Ok - had to see what happened if I ran 150us loops - well it worked on 2 T3.5s but get a bunch of bad last vals so its probably a bit much;
Code:
9628.00, #, #, #, #, #, #, #, #, #, #, #,87574,4368 [4469 ,10
9640.00, #, #, #, #, #, #, #, #, #, #, #,87575,4368 [4469 ,10
9652.00, #, #, #, #, #, #, #, #, #, #, #,87576,4368 [4469 ,10
9664.00, #, #, #, #, #, #, #, #, #, #, #,87577,4368 [4469 ,10
9676.00, #, #, #, #, #, #, #, #, #, #, #,87578,4368 [4469 ,10
9688.00, #, #, #, #, #, #, #, #, #, #, #,87579,4368 [4469 ,10
9700.00, #, #, #, #, #, #, #, #, #, #, #,87580,4368 [4469 ,10

Both t3.5s at 168Mhz
 
yeah, 180 you'll get intermittant... thats why mostly i used ~ 200 or higher, which on 3.5 results in 4.7k Hz, Tim can push 6K im sure, since 10uS F&F loops() makes a difference of ~ 300Hz
 
Mike, I loaded up the "simple" wire test demo I made you "as-is" and it's working.....

https://forum.pjrc.com/threads/50008-Project-SPI_MSTransfer?p=175770&viewfull=1#post175770
#1279 ...

Code:
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test... 
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
 
I had to try at 180 just out of curiosity. Never tried going that low before - was interesting.


EDIT: Yeah - I was getting ready to test it on the T3.5s when I found the 3.5 problem but not that's resolved I can go back and try it.
 
After the CB list,push_back,pop_front mods yesturday i let the SPI_MST run overnight @ stock cpu speeds and 30MHz :)

Code:
11628.00, #, #, #, #, #, #, #, #, #, #, #,384787748,77582 [5006 ,10
11640.00, #, #, #, #, #, #, #, #, #, #, #,384787749,77582 [5006 ,10
11652.00, #, #, #, #, #, #, #, #, #, #, #,384787750,77582 [5006 ,10
11664.00, #, #, #, #, #, #, #, #, #, #, #,384787751,77582 [5006 ,10
11676.00, #, #, #, #, #, #, #, #, #, #, #,384787752,77582 [5006 ,10
11688.00, #, #, #, #, #, #, #, #, #, #, #,384787753,77582 [5006 ,10
11700.00, #, #, #, #, #, #, #, #, #, #, #,384787754,77582 [5006 ,10
11712.00, #, #, #, #, #, #, #, #, #, #, #,384787755,77582 [5006 ,10
11724.00, #, #, #, #, #, #, #, #, #, #, #,384787756,77582 [5006 ,10
11736.00, #, #, #, #, #, #, #, #, #, #, #,384787757,77582 [5006 ,10
11748.00, #, #, #, #, #, #, #, #, #, #, #,384787758,77582 [5006 ,10
11760.00, #, #, #, #, #, #, #, #, #, #, #,384787759,77582 [5006 ,10

Code:
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==52
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==51
F&F (OT=0) OT_CALC==100  micros() _time==51
 
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Morning tonton81,
Guess another update bites the dust :) Guess its almost time to update the library on GitHub again :)

Hows the LC stuff going?

Mike
 
cant do LC...

currently the library handles 16bit data,, where the LC registers for SPI are 8bit for low and 8bit for high

this would require rewriting a very good portion of the library and several ifdefs just to make it work

example

the SPI0_PUSHR_SLAVE and the SPI0_POPR register is the same on the LC, but you must read/write to both entries for the 16bits to work
SPI0_DL and SPI0_DH, it wouldn’t be worth the hastle to change everything on how MST works just to support that specific model...
 
Got it and you are absolutely right. Was just curious. Saw a few posts about but wasn't sure it was a no go.
 
I've updated github with the latest SPI_MST and circular buffer as per recent posts :) Also added T list(); as a supported method for the Ring Buffer of the readme.md file for Circular_Buffer repo, which gained push_back and pop_front for float queue array capability
 
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Hi Tony.

Think you forgot to modify your begin function to adjust for T3.5/3.6 vs 3.2. The following should do the trick.

Mike

Code:
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
    SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock
    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS; // stop
    SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15) & SPI0_CTAR0_SLAVE & (~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25);
    SPI0_RSER = 0x00020000;
    CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
    CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN2_CONFIG =  PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS; // start
    NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
#else
    SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock

    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
    SPI0_MCR = 0x00000000;
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;

    SPI0_CTAR0_SLAVE = 0;
    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
    SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15);
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;

    SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
    SPI0_CTAR0_SLAVE = SPI0_CTAR0_SLAVE & ~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25;
    SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;

    SPI0_RSER = 0x00020000;

    CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
    CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
    CORE_PIN2_CONFIG =  PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
    NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
    NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
#endif
 
But the 3.5 is working at 30MHz with the fixed one for the 3.2... Yesturday I had a bad ground link and added 2 grounds and it worked :eek:
 
Funny, it was the only way that the 3.5/3.2 worked for me. I will have to give it another try. I'll try the 2 gnd trick just in case. Working on the house again, not the weather is nice :(.
 
Guys, I did something crazy, probably will be used, or not, when I added the list() method, I just made a ::remove(indice) method:

Code:
  Circular_Buffer<uint8_t, 4, 6> ca;
  uint8_t buf[6] = { 0, 1, 2, 3, 4, 5 };
  uint8_t buf1[6] = { 6, 7, 8, 9, 10, 11 };
  uint8_t buf2[6] = { 12, 13, 14, 15, 16, 17 };
  uint8_t buf3[6] = { 18, 19, 20, 21, 22, 23 };
  uint8_t buf4[6] = { 24, 25, 26, 27, 28, 29 };
  uint8_t buf5[6] = { 30, 31, 32, 33, 34, 35 };
  uint8_t buf6[6] = { 36, 37, 38, 39, 40, 41 };
  ca.push_back(buf, 6);
  ca.push_back(buf1, 6);
  ca.push_back(buf2, 6);
  ca.push_back(buf3, 6);
  ca.push_back(buf4, 6);
  ca.push_back(buf5, 6);
  ca.push_back(buf6, 6);

  ca.list();
  ca.[COLOR="#FF0000"]remove(3);[/COLOR]
  ca.list();
  while (1);

what do you think?

Code:
Circular Array Buffer Queue Size: 4 / 4

First Entry: 18    19    20    21    22    23    (6 entries.)
Last Entry:  36    37    38    39    40    41    (6 entries.)

[Indice]      [Entries]

    3		[COLOR="#FF0000"]18	19	20	21	22	23	[/COLOR](6 entries.)
    0		24	25	26	27	28	29	(6 entries.)
    1		30	31	32	33	34	35	(6 entries.)
    2		36	37	38	39	40	41	(6 entries.)
HEAD: 0
POS: 3

Circular Array Buffer Queue Size: 3 / 4

First Entry: 24    25    26    27    28    29    (6 entries.)
Last Entry:  36    37    38    39    40    41    (6 entries.)

[Indice]      [Entries]

    0		24	25	26	27	28	29	(6 entries.)
    1		30	31	32	33	34	35	(6 entries.)
    2		36	37	38	39	40	41	(6 entries.)


This:
Code:
 [COLOR="#FF0000"] ca.remove(2);[/COLOR]

Code:
Circular Array Buffer Queue Size: 4 / 4

First Entry: 18    19    20    21    22    23    (6 entries.)
Last Entry:  36    37    38    39    40    41    (6 entries.)

[Indice]      [Entries]

    3		18	19	20	21	22	23	(6 entries.)
    0		24	25	26	27	28	29	(6 entries.)
    1		30	31	32	33	34	35	(6 entries.)
    2		36	37	38	39	40	41	(6 entries.)
HEAD: 3
POS: 2

Circular Array Buffer Queue Size: 3 / 4

First Entry: 18    19    20    21    22    23    (6 entries.)
Last Entry:  30    31    32    33    34    35    (6 entries.)

[Indice]      [Entries]

    0		18	19	20	21	22	23	(6 entries.)
    1		24	25	26	27	28	29	(6 entries.)
    2		30	31	32	33	34	35	(6 entries.)
 
Finally got a chance to try out the new library with the T3.5/T3.2 combo. With the T3.5 as master at 168Mhz and the T3.2 as the slave at 120 Mhz with a 30Mhz bus speed still had the same issue as I described in post #1355. I also added a second ground line. At 24Mhz it works fine no problems whatsoever.

On 2T3.5s at 168Mhz and 30Mhz SPI bus I get nothing on the slave and just F&F messages on the master.

Mike

EDIT: Just saw your post on the remove method. Reminds of something but it was implemented a lot more complicated way.
 
Btw, now we can find and remove/edit queues in any location (not just front or back), I just need to add a find function :p

am I creating a super ::list ? :p
 
Know it works fine for the T3.5/3.5 combo for sure - will do a double check for the T3.5/T.3.2 combo just to be on the save side. Will edit this post in about 10 minutes have to put it back in the new library.

Find method would be interesting.

EDIT:
am I creating a super ::list ? :p
Yes you are. Never seen all this contained in one library.

BTW. Finished retesting the 3.5/3.2 combo and it works. But just can't get over 24Mhz. Don't know how you got your 3.5/3.2 combo over 30Mhz spi speed.
 
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