defragster
Senior Member+
It this with T_3.2 as Master? At what F_CPU? For F_CPU at 96 then F_BUS is 48 and it won't work over 24 - per the spec. It might hit SPI of 30 MHz with OC to F_CPU==120 and F_BUS==60?
Yeah but we need to push 2 8bit registers SPI0_DL && SPI0_DH, and read them like the POPR, it's a 2 way register, but thats alot of ifdefs and code rewriting to adapt!
it's not as simple as a redefine...
9628.00, #, #, #, #, #, #, #, #, #, #, #,87574,4368 [4469 ,10
9640.00, #, #, #, #, #, #, #, #, #, #, #,87575,4368 [4469 ,10
9652.00, #, #, #, #, #, #, #, #, #, #, #,87576,4368 [4469 ,10
9664.00, #, #, #, #, #, #, #, #, #, #, #,87577,4368 [4469 ,10
9676.00, #, #, #, #, #, #, #, #, #, #, #,87578,4368 [4469 ,10
9688.00, #, #, #, #, #, #, #, #, #, #, #,87579,4368 [4469 ,10
9700.00, #, #, #, #, #, #, #, #, #, #, #,87580,4368 [4469 ,10
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
Size: 54 Slave: 43 Port: 0
Hello Mike, this is a test...
11628.00, #, #, #, #, #, #, #, #, #, #, #,384787748,77582 [5006 ,10
11640.00, #, #, #, #, #, #, #, #, #, #, #,384787749,77582 [5006 ,10
11652.00, #, #, #, #, #, #, #, #, #, #, #,384787750,77582 [5006 ,10
11664.00, #, #, #, #, #, #, #, #, #, #, #,384787751,77582 [5006 ,10
11676.00, #, #, #, #, #, #, #, #, #, #, #,384787752,77582 [5006 ,10
11688.00, #, #, #, #, #, #, #, #, #, #, #,384787753,77582 [5006 ,10
11700.00, #, #, #, #, #, #, #, #, #, #, #,384787754,77582 [5006 ,10
11712.00, #, #, #, #, #, #, #, #, #, #, #,384787755,77582 [5006 ,10
11724.00, #, #, #, #, #, #, #, #, #, #, #,384787756,77582 [5006 ,10
11736.00, #, #, #, #, #, #, #, #, #, #, #,384787757,77582 [5006 ,10
11748.00, #, #, #, #, #, #, #, #, #, #, #,384787758,77582 [5006 ,10
11760.00, #, #, #, #, #, #, #, #, #, #, #,384787759,77582 [5006 ,10
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==52
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==51
F&F (OT=0) OT_CALC==100 micros() _time==51
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS; // stop
SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15) & SPI0_CTAR0_SLAVE & (~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25);
SPI0_RSER = 0x00020000;
CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
CORE_PIN2_CONFIG = PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS; // start
NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
#else
SIM_SCGC6 |= SIM_SCGC6_SPI0; // enable slave clock
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
SPI0_MCR = 0x00000000;
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;
SPI0_CTAR0_SLAVE = 0;
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
SPI0_CTAR0_SLAVE = SPI_CTAR_FMSZ(15);
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;
SPI0_MCR |= SPI_MCR_HALT | SPI_MCR_MDIS;
SPI0_CTAR0_SLAVE = SPI0_CTAR0_SLAVE & ~(SPI_CTAR_CPOL | SPI_CTAR_CPHA) | 0x00 << 25;
SPI0_MCR &= ~SPI_MCR_HALT & ~SPI_MCR_MDIS;
SPI0_RSER = 0x00020000;
CORE_PIN14_CONFIG = PORT_PCR_MUX(2);
CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
CORE_PIN2_CONFIG = PORT_PCR_PS | PORT_PCR_MUX(2); // this uses pin 2 for the CS so Serial2 can be used instead.
NVIC_SET_PRIORITY(IRQ_SPI0, 1); // set priority
NVIC_ENABLE_IRQ(IRQ_SPI0); // enable CS IRQ
#endif
Circular_Buffer<uint8_t, 4, 6> ca;
uint8_t buf[6] = { 0, 1, 2, 3, 4, 5 };
uint8_t buf1[6] = { 6, 7, 8, 9, 10, 11 };
uint8_t buf2[6] = { 12, 13, 14, 15, 16, 17 };
uint8_t buf3[6] = { 18, 19, 20, 21, 22, 23 };
uint8_t buf4[6] = { 24, 25, 26, 27, 28, 29 };
uint8_t buf5[6] = { 30, 31, 32, 33, 34, 35 };
uint8_t buf6[6] = { 36, 37, 38, 39, 40, 41 };
ca.push_back(buf, 6);
ca.push_back(buf1, 6);
ca.push_back(buf2, 6);
ca.push_back(buf3, 6);
ca.push_back(buf4, 6);
ca.push_back(buf5, 6);
ca.push_back(buf6, 6);
ca.list();
ca.[COLOR="#FF0000"]remove(3);[/COLOR]
ca.list();
while (1);
Circular Array Buffer Queue Size: 4 / 4
First Entry: 18 19 20 21 22 23 (6 entries.)
Last Entry: 36 37 38 39 40 41 (6 entries.)
[Indice] [Entries]
3 [COLOR="#FF0000"]18 19 20 21 22 23 [/COLOR](6 entries.)
0 24 25 26 27 28 29 (6 entries.)
1 30 31 32 33 34 35 (6 entries.)
2 36 37 38 39 40 41 (6 entries.)
HEAD: 0
POS: 3
Circular Array Buffer Queue Size: 3 / 4
First Entry: 24 25 26 27 28 29 (6 entries.)
Last Entry: 36 37 38 39 40 41 (6 entries.)
[Indice] [Entries]
0 24 25 26 27 28 29 (6 entries.)
1 30 31 32 33 34 35 (6 entries.)
2 36 37 38 39 40 41 (6 entries.)
[COLOR="#FF0000"] ca.remove(2);[/COLOR]
Circular Array Buffer Queue Size: 4 / 4
First Entry: 18 19 20 21 22 23 (6 entries.)
Last Entry: 36 37 38 39 40 41 (6 entries.)
[Indice] [Entries]
3 18 19 20 21 22 23 (6 entries.)
0 24 25 26 27 28 29 (6 entries.)
1 30 31 32 33 34 35 (6 entries.)
2 36 37 38 39 40 41 (6 entries.)
HEAD: 3
POS: 2
Circular Array Buffer Queue Size: 3 / 4
First Entry: 18 19 20 21 22 23 (6 entries.)
Last Entry: 30 31 32 33 34 35 (6 entries.)
[Indice] [Entries]
0 18 19 20 21 22 23 (6 entries.)
1 24 25 26 27 28 29 (6 entries.)
2 30 31 32 33 34 35 (6 entries.)
Yes you are. Never seen all this contained in one library.am I creating a super ::list ?