I am working on a signal processing project to replace a current FPGA + level shifter design with a Teensy 3.5 in order to reduce parts count.
The input signals are +5V, but the few output signals can be 3v3 levels.
The current FPGA (and now Teensy) design must respond within 85 nanosecond of an input signal change to assert an appropriate output signal.
The Teensy ARM code and hardware (using input voltage level shifter buffers) successfully works with Teensy 3.6 at [F_CPU] 240 MHz and [F_BUS] 120 MHz, but would like to eliminate the need to use the 5 extra 5V --> 3v3 level-shifter chips.
'Scoping/logic analyzing the Teensy 3.5 at 120, 144, and 168 MHz reveals that the 3.5 is too slow, so overclocking to 240 MHz might be an option.
Does anybody have any [successful] experience with overclocking the '3.5 to this speed, or have other suggestions or options?
Bruce Ray
Wild Hare Computer Systems, Inc.
Boulder, Colorado USA
The input signals are +5V, but the few output signals can be 3v3 levels.
The current FPGA (and now Teensy) design must respond within 85 nanosecond of an input signal change to assert an appropriate output signal.
The Teensy ARM code and hardware (using input voltage level shifter buffers) successfully works with Teensy 3.6 at [F_CPU] 240 MHz and [F_BUS] 120 MHz, but would like to eliminate the need to use the 5 extra 5V --> 3v3 level-shifter chips.
'Scoping/logic analyzing the Teensy 3.5 at 120, 144, and 168 MHz reveals that the 3.5 is too slow, so overclocking to 240 MHz might be an option.
Does anybody have any [successful] experience with overclocking the '3.5 to this speed, or have other suggestions or options?
Bruce Ray
Wild Hare Computer Systems, Inc.
Boulder, Colorado USA