Teensy 3.2 3.5 3.6 cache sizes

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vladn

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Does anyone know the ARM CPUs cache sizes used in 3.2 / 3.5 / 3.6 Teensy models ?
For some reason I can't find the numbers in the reference manuals.
 
Thanks a lot !
There is surprisingly huge step between K64 and K66. Just curious - are there reference documents that mention cache size explicitly (I went thru manuals and electrical specs and found no info)
 
I understand that the cache subsystem in Kinetis is part of a flash controller. Looking at the FMC memory maps suggests that K64 has 128 byte cache and K66 has 256 byte cache. Please check the K64 manual - pages 633..636, and the K66 manual - pages 704..708. Both manuals are on this site:
https://www.pjrc.com/teensy/datasheets.html

Both K64 and K66 have 4way/4set associative cache (16 blocks total). But K64 has a 64bit block and k66 has a 128bit block. So we get 16x8bytes=128bytes for K64 and 16x16bytes=256bytes for K66.
Please correct me if I am wrong...
 
Continuing cache size investigation it looks like Teensy 3.2/3.2 has 256byte flash controller cache. The structure is 4way/8set (32 blocks) of 64bit each. So the total is 32x8bytes=256bytes.
 
are there reference documents that mention cache size explicitly (I went thru manuals and electrical specs and found no info)

It's buried deep within the manual.

https://www.pjrc.com/teensy/K66P144M180SF5RMV2.pdf

The 8K cache features are described in detail starting on page 681.

The actual cache size is documented near the bottom of page 695. Easy to find, right?!

It's also worth noticing the entire RAM is effectively single cycle and doesn't use the cache. Since we're not using an external memory chip (which would burn up a huge number of the pins), the entire 8K cache gets used for the flash memory.

Yes, there's also a tiny cache built into the flash controller on all these chips. On Teensy 3.0-3.5, that's the only cache. This big 8K cache is only on Teensy 3.6.
 
Got it ! Thanks Paul !
Just few hours ago NXP tech support was convincingly telling me that K66 has NO additional cache besides the tiny FMC one. That is what happens when design travels the path of multiple company M/A.

I was evaluating the relative benefits of 3.5 vs 3.6 for my design that does not require high clock speeds (48MHz works just fine), but I want the convenience and efficiency of the FPU for DSP functions and I am at 100% pin usage on 3.2 and may need few more. I got 3.6 from you, but it looks like 3.5 is just what I need going forward. Basically the figure of merit for me is Jouls of energy per single 256point complex FP FFT or a complex FP FIR and such.
 
Not the first time it happened to me in this profession :)

That 8k cache in K66 would be a significant benefit when operating close to nominal speeds. When running at 48MHz there should be just one wait state for flash access on a FMC cache miss (unless FMC pipelines the flash path). Hence I am leaning towards K64 for my DSP RX project.

However I think I am right that K64 has only 128bytes in the FMC cache, half that of a K20 in 3.2. If I am correct then perhaps the tech spec table should reflect that, and also that K66 has two separate caches 256byte + 8192byte. It may be a helpful hint for many Teensy users choosing between 3.5 and 3.6.
 
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