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Thread: Teensy 4.0 (hypothetical) pin assignments

  1. #176
    Senior Member PaulStoffregen's Avatar
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    Oh wow, I totally missed AIPS-5 in the new memory map!

    The only mention of faster GPIO seems to be the clocks on page 1093 of the 1060 manual.

  2. #177
    Senior Member+ Frank B's Avatar
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    I wonder what additional hidden features the old T3.x, and new T4 have (like the gpio digital filters we found)

  3. #178
    Senior Member+ Frank B's Avatar
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    The errata of the different variants show surprising coincidences.
    I think it's quite likely that they have the same silicon, but differently configured by fuses.

    1020:https://www.nxp.com/docs/en/errata/IMXRT1020CE.pdf
    1050:https://www.nxp.com/docs/en/errata/IMXRT1050CE.pdf
    1060:https://www.nxp.com/docs/en/nxp/errata/IMXRT1060CE.pdf

    Perhaps we will find surprising details by comparing the reference manuals.
    Last edited by Frank B; 10-27-2018 at 10:05 AM.

  4. #179
    Senior Member+ Frank B's Avatar
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    @Paul: Teensy 4: Will the MQS be available? Not as good as DACs, but OK for a huge number of applications.


    Code:
    9.1.2
    
    Medium Quality Sound (MQS)
    
    MQS is used to generate medium quality audio via a standard GPIO in the pinmux. The
    
    user can connect stereo speakers or headphones to a power amplifier without an
    
    additional DAC chip.
    
    •  2-channel, LSB-valid 16 bit, MSB shift-out first serial data (sdata)
    
    •  Frame sync aligned with the left channel data
    
    •  44 kHz or 48 kHz I2S signals from SAI3
    
    •  SNR target as no more than 20 dB for the signals below 10 kHz
    
    •  Signals over 10 kHz have worse THD+N values
    

    edit: I haven't seen it on the block diagrams yet.

    If I had to choose between additional serial interfaces and MQS, I would choose MQS

    Edit: Pads are:
    Right channel: GPIO_AD_B0_04 or GPIO_B0_00 or GPIO_EMC_13
    Let channel:
    GPIO_EMC_14 or GPIO_B0_01 or GPIO_AD_B0_05


    Edit: You already have them on your list in post #1, perfect!
    Code:
    Name      BGA  Power  Def  Analog       ATL0            ALT1            ALT2            ALT3            ALT4            ALT5            ALT6            ALT7
    ----      ---  -----  ---  ------       ----            ----            ----            ----            ----            ----            ----            ----
    B0_00     D7   GPIO   ALT5              LCD_CLK         QTIMER1_TIMER0  MQS_RIGHT       SPI4_CS0        FlexIO2:0       GPIO2:0         SEMC_CSX1       -               Arduino 10
    B0_01     E7   GPIO   ALT5              LCD_ENABLE      QTIMER1_TIMER1  MQS_LEFT        SPI4_MISO       FlexIO2:1       GPIO2:1         SEMC_CSX2       -               Arduino 12
    Last edited by Frank B; 10-27-2018 at 10:59 AM.

  5. #180
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Frank B View Post
    Edit: You already have them on your list in post #1, perfect!
    But only perfect if you're not using SPI, or using it without MISO.

  6. #181
    Senior Member PaulStoffregen's Avatar
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    Opps, I just realized msg #20 doesn't have 1 change I made some time ago. Here's the latest pin list.

    Code:
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
     0     AD_B0_03   1.3   UART6_RX       3:CS0   PWM1_X1  2_RX             IO-17
     1     AD_B0_02   1.2   UART6_TX       3:MISO  PWM1_X0  2_TX             IO-16
     2     EMC_04     4.4                          PWM4_A2        2:TX_DATA  IO-06   1:4
     3     EMC_05     4.5                          PWM4_B2        2:TX_SYNC  IO-07   1:5
     4     EMC_06     4.6                          PWM2_A0        2:TX_BCLK  IO-08   1:6
     5     EMC_07     4.7                          PWM2_B0        2:MCLK     IO-09   1:7
     6     B1_01      2.17  UART4_RX               PWM1_B3        1:TX_DATA  IO-15   2:17,3:17
     7     B1_00      2.16  UART4_TX               PWM1_A3        1:RX_DATA  IO-14   2:16,3:16
     8     B0_10      2.10                         PWM2_A2,QT4_1  1:TX3_RX1          2:10
     9     B0_11      2.11                         PWM2_B2,QT4_2  1:TX2_RX2          2:11
    10     B0_00      2.0                  4:CS0   QT1_0          MQS_RIGHT          2:0     
    11     B0_02      2.2                  4:MOSI  QT1_2    1_TX                     2:2
    12     B0_01      2.1                  4:MISO  QT1_1          MQS_LEFT           2:1     
    13     B0_03      2.3                  4:SCK   QT2_0    1_RX                     2:3
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    14/A0  AD_B1_02   1.18  UART2_TX               QT3_2          SPDIF_OUT          3:2     A1:7,A2:7
    15/A1  AD_B1_03   1.19  UART2_RX               QT3_3          SPDIF_IN           3:3     A1:8,A2:8
    16/A2  AD_B1_07   1.23  UART3_RX  3_SCL                       SPDIF_EXTCLK       3:7     A1:12,A2:12
    17/A3  AD_B1_06   1.22  UART3_TX  3_SDA                       SPDIF_LOCK         3:6     A1:11,A2:11
    18/A4  AD_B1_01   1.17   2_cts    1_SDA        QT3_1                             3:1     A1:6,A2:6
    19/A5  AD_B1_00   1.16            1_SCL        QT3_0                             3:0     A1:5,A2:5
    20/A6  AD_B1_10   1.26  UART8_TX                              1:RX_SYNC          3:10    A1:15,A2:15
    21/A7  AD_B1_11   1.27  UART8_RX                              1:RX_BCLK          3:11    A1:0,A2:0
    22/A8  AD_B1_08   1.24                         PWM4_A0  1_TX                     3:8     A1:13,A2:13
    23/A9  AD_B1_09   1.25                         PWM4_A1  1_RX  1:MCLK             3:9     A1:14,A2:14
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    24/A10 AD_B0_12   1.12  UART1_TX  4_SCL        PWM1_X2                                   A1:1  
    25/A11 AD_B0_13   1.13  UART1_RX  4_SDA        PWM1_X3,GPT1_CLK                          A1:2
    26/A12 AD_B1_14   1.30                 3:MOSI                 1:TX_BCLK          3:14    A2:3  
    27/A13 AD_B1_15   1.31                 3:SCK                  1:TX_SYNC          3:15    A2:4  
    28     EMC_32     3.18  UART7_RX               PWM3_B1
    29     EMC_31     4.31  UART7_TX       1:cs1   PWM3_A1
    30     EMC_24     4.24  UART5_RX               PWM1_B0
    31     EMC_23     4.23  UART5_TX               PWM1_A0
    32     B0_12      2.12                                        1:TX1_RX3  IO-10   2:12
    33     EMC_08     4.8                          PWM2_A1        2:RX_DATA  IO-17   1:8
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    And here are pins *NOT* used, but temping possibilities if something from the list gets cut

    Code:
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
           AD_B0_15   1.15                                  3_RX,2_RX                        A1:4  
           AD_B0_14   1.14   1_cts                          3_TX,2_TX        I-24            A1:3  
           EMC_37     3.23                         GPT1_3   3_RX  3:MCLK     I-23
           EMC_36     3.22                         GPT1_2   3_TX  3:TX_DATA  I-22
           B0_04      GPIO            2_SCL        QT2_1                             2:4
           B0_05      GPIO            2_SDA        QT2_2                             2:5
           AD_B0_01   GPIO                 3:MOSI                            IO-15
           AD_B0_00   GPIO                 3:SCK                             IO-14
           EMC_00     GPIO                 2:SCK   pwm4_a0                   I-02    1:0
           EMC_02     GPIO                 2:MOSI  pwm4_a1                   IO-04   1:2
           EMC_03     GPIO                 2:MISO  PWM4_B1                   IO-05   1:3
           B1_03      GPIO                 4:CS1   PWM2_B3        1:TX_SYNC  IO-17   2:19
           B1_02      GPIO                 4:CS2   PWM2_A3        1:TX_BCLK  IO-16   2:18
           EMC_26     GPIO  UART6_RX               PWM1_B1                           1:12
           EMC_25     GPIO  UART6_TX               PWM1_A1
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------

  7. #182
    Senior Member brtaylor's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Opps, I just realized msg #20 doesn't have 1 change I made some time ago. Here's the latest pin list.

    Code:
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
     0     AD_B0_03   1.3   UART6_RX       3:CS0   PWM1_X1  2_RX             IO-17
     1     AD_B0_02   1.2   UART6_TX       3:MISO  PWM1_X0  2_TX             IO-16
     2     EMC_04     4.4                          PWM4_A2        2:TX_DATA  IO-06   1:4
     3     EMC_05     4.5                          PWM4_B2        2:TX_SYNC  IO-07   1:5
     4     EMC_06     4.6                          PWM2_A0        2:TX_BCLK  IO-08   1:6
     5     EMC_07     4.7                          PWM2_B0        2:MCLK     IO-09   1:7
     6     B1_01      2.17  UART4_RX               PWM1_B3        1:TX_DATA  IO-15   2:17,3:17
     7     B1_00      2.16  UART4_TX               PWM1_A3        1:RX_DATA  IO-14   2:16,3:16
     8     B0_10      2.10                         PWM2_A2,QT4_1  1:TX3_RX1          2:10
     9     B0_11      2.11                         PWM2_B2,QT4_2  1:TX2_RX2          2:11
    10     B0_00      2.0                  4:CS0   QT1_0          MQS_RIGHT          2:0     
    11     B0_02      2.2                  4:MOSI  QT1_2    1_TX                     2:2
    12     B0_01      2.1                  4:MISO  QT1_1          MQS_LEFT           2:1     
    13     B0_03      2.3                  4:SCK   QT2_0    1_RX                     2:3
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    14/A0  AD_B1_02   1.18  UART2_TX               QT3_2          SPDIF_OUT          3:2     A1:7,A2:7
    15/A1  AD_B1_03   1.19  UART2_RX               QT3_3          SPDIF_IN           3:3     A1:8,A2:8
    16/A2  AD_B1_07   1.23  UART3_RX  3_SCL                       SPDIF_EXTCLK       3:7     A1:12,A2:12
    17/A3  AD_B1_06   1.22  UART3_TX  3_SDA                       SPDIF_LOCK         3:6     A1:11,A2:11
    18/A4  AD_B1_01   1.17   2_cts    1_SDA        QT3_1                             3:1     A1:6,A2:6
    19/A5  AD_B1_00   1.16            1_SCL        QT3_0                             3:0     A1:5,A2:5
    20/A6  AD_B1_10   1.26  UART8_TX                              1:RX_SYNC          3:10    A1:15,A2:15
    21/A7  AD_B1_11   1.27  UART8_RX                              1:RX_BCLK          3:11    A1:0,A2:0
    22/A8  AD_B1_08   1.24                         PWM4_A0  1_TX                     3:8     A1:13,A2:13
    23/A9  AD_B1_09   1.25                         PWM4_A1  1_RX  1:MCLK             3:9     A1:14,A2:14
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    24/A10 AD_B0_12   1.12  UART1_TX  4_SCL        PWM1_X2                                   A1:1  
    25/A11 AD_B0_13   1.13  UART1_RX  4_SDA        PWM1_X3,GPT1_CLK                          A1:2
    26/A12 AD_B1_14   1.30                 3:MOSI                 1:TX_BCLK          3:14    A2:3  
    27/A13 AD_B1_15   1.31                 3:SCK                  1:TX_SYNC          3:15    A2:4  
    28     EMC_32     3.18  UART7_RX               PWM3_B1
    29     EMC_31     4.31  UART7_TX       1:cs1   PWM3_A1
    30     EMC_24     4.24  UART5_RX               PWM1_B0
    31     EMC_23     4.23  UART5_TX               PWM1_A0
    32     B0_12      2.12                                        1:TX1_RX3  IO-10   2:12
    33     EMC_08     4.8                          PWM2_A1        2:RX_DATA  IO-17   1:8
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    And here are pins *NOT* used, but temping possibilities if something from the list gets cut

    Code:
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
           AD_B0_15   1.15                                  3_RX,2_RX                        A1:4  
           AD_B0_14   1.14   1_cts                          3_TX,2_TX        I-24            A1:3  
           EMC_37     3.23                         GPT1_3   3_RX  3:MCLK     I-23
           EMC_36     3.22                         GPT1_2   3_TX  3:TX_DATA  I-22
           B0_04      GPIO            2_SCL        QT2_1                             2:4
           B0_05      GPIO            2_SDA        QT2_2                             2:5
           AD_B0_01   GPIO                 3:MOSI                            IO-15
           AD_B0_00   GPIO                 3:SCK                             IO-14
           EMC_00     GPIO                 2:SCK   pwm4_a0                   I-02    1:0
           EMC_02     GPIO                 2:MOSI  pwm4_a1                   IO-04   1:2
           EMC_03     GPIO                 2:MISO  PWM4_B1                   IO-05   1:3
           B1_03      GPIO                 4:CS1   PWM2_B3        1:TX_SYNC  IO-17   2:19
           B1_02      GPIO                 4:CS2   PWM2_A3        1:TX_BCLK  IO-16   2:18
           EMC_26     GPIO  UART6_RX               PWM1_B1                           1:12
           EMC_25     GPIO  UART6_TX               PWM1_A1
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Pin    Name       GPIO  Serial    I2C  SPI     PWM      CAN   Audio      XBAR    FlexIO  Analog
    ---    ----       ----  ------    ---  ---     ---      ---   ----       ----    ------  ------
    Thanks for the layout, I somehow missed it! Paul, any reason UART4 is on pins 6 and 7? If they got bumped to pins 7 and 8, then UART 4 on Teensy 4 would match up with UART 3 on Teensy 3.

  8. #183
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    Quote Originally Posted by brtaylor View Post
    Thanks for the layout, I somehow missed it! Paul, any reason UART4 is on pins 6 and 7? If they got bumped to pins 7 and 8, then UART 4 on Teensy 4 would match up with UART 3 on Teensy 3.
    as follow-on: I assume routing has not been carried out, so pin numbers may change, correct?

  9. #184
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    Ok based on post #182 this is what it may look like, I like pictures, easier for me. Actual pin assignments may change, just for quick ref:
    Click image for larger version. 

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    Click image for larger version. 

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ID:	15041

    If I missed something or labeled something wrong please let me know. I probably did - there is a lot going on with the pin assignments for the T4

  10. #185
    Senior Member+ Frank B's Avatar
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    Oh, the SD-Slot would be a dream - have I missed something? If Paul could manage to place the pads at least, if there is enough room...

  11. #186
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by WMXZ View Post
    as follow-on: I assume routing has not been carried out,
    It has, at least initial routing on a slightly larger 4 layer board.

    We're actually on the 2nd rev of the prototype. The changes from the 1st rev, and the work I'm doing right now, involves how we're going to recover from user programs that do "bad" things.

    so pin numbers may change, correct?
    Some changes are still possible.

    Quote Originally Posted by mjs513 View Post
    I like pictures, easier for me
    The bottom side pads can't possibly be in the center of the board underneath the BGA.

    Quote Originally Posted by Frank B View Post
    Oh, the SD-Slot would be a dream - have I missed something? If Paul could manage to place the pads at least, if there is enough room...
    I do currently have the 8 pads in the design. They create a routing nightmare! I probably can't place them at the ideal location, but trying....

  12. #187
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    The bottom side pads can't possibly be in the center of the board underneath the BGA.
    Never thought about that one. In that case not really sure how to place them - for now guess it will have to remain notional. I will modify it to show what will be on the bottom side. Matter of fact should have put notional on the images to begin with.

  13. #188
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by mjs513 View Post
    Never thought about that one. In that case not really sure how to place them - for now guess it will have to remain notional. I will modify it to show what will be on the bottom side. Matter of fact should have put notional on the images to begin with.
    That came up in post #89 … Image below has an older card MOCK UP …. emphasis added below this time
    Quote Originally Posted by defragster View Post
    ...
    Paul has noted what he expects he can present on the 1.4" T_3.2 sized board. One thing mjs513's mock up doesn't express - AFAIK the MCU package is like the K66 on the T_3.6. It fits pin to pin on the board's middle area and creates a no go region underneath where the BGA signals are routed. As note on the larger T_3.6 - to route the pins takes all the layers and putting a round hole through violates usable space on all of them.

    Here is a quick update showing some of the scale effect of that updated on the image from above with a clip of the T_3.6 bottom. Not presenting another couple dozen pins like the T_3.6 may make it somewhat less busy - but still not open to more round pins and having any hole free pads presented:
    Last edited by defragster; 10-29-2018 at 08:56 AM.

  14. #189
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    Quote Originally Posted by defragster View Post
    AFAIK the MCU package is like the K66 on the T_3.6. It fits pin to pin on the board's middle area (...)
    Correct me if I'm wrong: The outer dimension is the same (12x12mm) but it can't be pin to pin due to the 196pin BGA with 0.8mm pitch of the RT1050/-60 compared to the 144/1.0 of the K66? Or is there a package with less pins which I missed?

    Quote Originally Posted by mjs513
    I like pictures
    So do I. Maybe you should put something in the image which shows that these are not yet real. Just in case some heavily motivated picture search algorithm presents them and confuses people ;-)

  15. #190
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    Quote Originally Posted by MichaelB View Post
    So do I. Maybe you should put something in the image which shows that these are not yet real. Just in case some heavily motivated picture search algorithm presents them and confuses people ;-)
    To add: and it represents the spirit of Paul's repeated request, of not showing pictures before shipping the final products. (I know they are T3.2's and not T4, but as MichaelB notes, pictures may confuse or even be misused)
    Last edited by WMXZ; 10-29-2018 at 06:29 AM.

  16. #191
    Senior Member+ defragster's Avatar
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    Indeed looks like 12x12 mm instead of 13x13 of K64/k66 - not sure that helps anything but PJRC routing.

    No pics was made clear to those getting Beta Boards for T_3.5/3.6 - and limited exposure of final summary info …

  17. #192
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    Quote Originally Posted by PaulStoffregen View Post
    I do currently have the 8 pads in the design. They create a routing nightmare! I probably can't place them at the ideal location, but trying....
    As long they are easily accessible for a pin-extension board with build in uSD (or multiple uSD) cards!

    Q: are there bottom-side components, that would inhibit flash mounting?

  18. #193
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    @defragster. Yeah - went back and remembered you said and showed that before. Also, as I mentioned these images were notional based on the pins-functions posted on the original post 20 and now updated in post 184. Yes you are right that I need to put some note so others don't take it as anything else. Plain forgot.

    No pics was made clear to those getting Beta Boards for T_3.5/3.6 - and limited exposure of final summary info
    Tim, I didn't think I was violating Paul's desire to show "no pics" and limit exposure of final info. Since the title of this thread was "Teensy 4.0 (hypothetical) pin assignments" the images were just tool for visualizing what was posted in a hypothetical pin assignment. So, should I figure out a way just to delete the pics or create and updated one with your recommended note and add just hypothetical. How do I correct.

  19. #194
    Senior Member+ defragster's Avatar
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    For K66 beta Paul's admonition was this as beta boards were selectively shipped:
    Quote Originally Posted by Paul View Post
    ...
    I'd like to ask everyone to please avoid posting photos of the boards, and to keep all conversation on this forum thread. I'm trying to allow openness and access to technical information while avoiding premature promotion & vaporware. Hopefully a text-only forum thread is a good compromise. Please don't post pictures, especially on social networks, until we've finalized a page on the website (with photos) for ordering the final board.
    Mock Card was 100+ posts back - I've not seen notes on T_4 - though nobody wants PJRC beaten to market with a copy his own device.

  20. #195
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    Understood. To avoid any misconceptions or misuse will cease and desist with any further updates or posting of images.

  21. #196
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by defragster View Post
    Indeed looks like 12x12 mm instead of 13x13 of K64/k66 - not sure that helps anything but PJRC routing.
    NXP very recently added the 12x12 mm size (0.8 mm pitch). Initially they said it would be only 10x10 (0.65 mm pitch), so that's the size we're using. Turns out the 10x10 size works pretty well for the Teensy form factor, allowing enough room to put both crystals on the board without resorting to the much more expensive crystals in smaller size packages.

    The 10x10 and 12x12 sizes have the same pinout.

    The 13x13 size (1.0 mm pitch) on Teensy 3.5 & 3.6 is a completely different pinout.

  22. #197
    Senior Member+ defragster's Avatar
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    Now a 1064 with 4 MB on chip flash:
    i.MX RT Series Crossover Processor Fact Sheet (REV 4) updated
    PDF 185.1 kB IMXRTSERIESFS 29 Oct 2018

    Nice, 10x10 mm does leave you more room for flexibility.

  23. #198
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by WMXZ View Post
    Q: are there bottom-side components
    Yes. These new chips absolutely require decoupling capacitors on the bottom side underneath the BGA.

  24. #199
    Senior Member+ KurtE's Avatar
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    Wondering if with these pins you will be able to configure an Ethernet adapter?

    Looks like the ENET section defines something like 26 signals... Have not looked through here enough to know if you really need all of them?

  25. #200
    Senior Member PaulStoffregen's Avatar
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    Nope, sadly we're not going to get a RMII ethernet port on this pinout.

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