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Thread: Teensy 4.0 (hypothetical) pin assignments

  1. #201
    Senior Member+ Frank B's Avatar
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    Quote Originally Posted by defragster View Post
    Now a 1064 with 4 MB on chip flash:
    i.MX RT Series Crossover Processor Fact Sheet (REV 4) updated
    PDF 185.1 kB IMXRTSERIESFS 29 Oct 2018
    Oh.... that's very interesting. It would mean to have more space on the board.. and I doubt it uses quad-spi or any other serial protocol.
    Did you find any additional information?

  2. #202
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by Frank B View Post
    Oh.... that's very interesting. It would mean to have more space on the board.. and I doubt it uses quad-spi or any other serial protocol.
    Did you find any additional information?
    Oh indeed … Change in 'Block Diagram' and then the table below with the '1060/1064' column in that FRESH updated doc was all I found - nothing more as I searched around. I'm wondering if it would require the larger 12x12 package or not - but it would allow dropping (replacing) the external flash part and get rid of the qspi interface to flash stored code/data - even with some added waits, it would make the memory map flat. The 1060 can XIP from flash - but that has got to be a kludge with read/cache under the covers.

  3. #203
    Senior Member+ defragster's Avatar
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    Just re-reading between the lines on this post:

    Quote Originally Posted by PaulStoffregen View Post
    NXP very recently added the 12x12 mm size (0.8 mm pitch). Initially they said it would be only 10x10 (0.65 mm pitch), so that's the size we're using.
    ...

    Maybe the 12x12 was "very recently added" to provide area to hold the 4 MB Flash area for a 1064?

    3.1.1. External memory versus FlexRAM memory access consideration The i.MX RT10xx devices do not have embedded flash (RT1064 includes serial SPI flash as SIP).

    Some distributors show part - but no details on - though ones that showed were 10x10 package : MIMXRT1064DVL6A and MIMXRT1064DVL5A ? In stock Jan 2019

    RT1064 includes serial SPI flash as SIP … still SPI >> "A System-In-Package (SIP) is a further level of integration where multiple dice are integrated inside a single package."

    And there is a 1064 EVAL kit for $137 at DigiKey, the one for 1060 is $100 - no information provided.

  4. #204
    Senior Member PaulStoffregen's Avatar
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    I'm pretty sure they added the 12x12 size because they heard from customers (much larger than PJRC) that the 10x10 requires a more expensive PCB process. Early on I mentioned this to their marketing manager. He was unfazed at the time and referred me to their (then incorrect) materials about the PCB requirements. When they released their first eval boards, even pointing out their board used significantly smaller traces, annular rings and drill sizes that their marketing material claimed didn't seem to get through. I've spent the last several months working with that 10x10 package and it is tough.

    I'm pretty sure they heard this same feedback over and over from other customers. Probably from very large customers!

    The 0.8 mm pitch used on the 12x12 size really is the "sweet spot" for the normal specs of 4 layer PCBs. There are apparently a bunch of "IPC class 2" guidelines for PCB specs... the sort of thing you'd see a large corporation state as an arbitrary requirement. I'm pretty sure 10 mil drill and 5 mil annular ring (for non-laser vias) are in those guidelines. There's just no way to use the 10x10 size with those specs.

    Teensy4 will be using a 6 layer board with 8 mil drill vias, having 4 mil annular ring on the top layer (only inside the BGA) and 5 mil annular ring on the other 5 layers. This is based on quite a bit of negotiation with our PCB vendor, especially what they can accomplish with mechanical drilling. With those specs, routing all the BGA pins is impossible. So are a power & ground planes connecting to all the required places. But Teensy won't bring all the pins out. A huge part of the work I did a couple months ago was a special scheme which arranges the vias into rows aligned on every other BGA row. This less-than-ideal via row placement makes the routing extremely hard, but it buys room the 5 mil annular ring on other layers and for the power planes and traces to route through the center of the board on 2 of the 3 routing layers.

    With 0.8 mm ball pitch, you can use 19.5 mil diameter vias (very close to 10 mil drill & 5 mil annular ring) and have 12 mils between them, allowing a 4 mil trace to pass through with 4 mil clearance to each via. When another larger Teensy is made with more pins & features, I'll certainly go with the 12x12 size.

    The 10x10 size is really, really hard to use without very special (and very expensive) PCB process like laser drill. We're going to make it work on Teensy 4.0, but only by using a subset of the pins and this special arrangement of vias on alternating rows.

  5. #205
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    Quote Originally Posted by PaulStoffregen View Post
    The 10x10 size is really, really hard to use without very special (and very expensive) PCB process like laser drill. We're going to make it work on Teensy 4.0, but only by using a subset of the pins and this special arrangement of vias on alternating rows.
    that is what makes teensy so special! I look forward for T4.0!

  6. #206
    Senior Member brtaylor's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    I'm pretty sure they added the 12x12 size because they heard from customers (much larger than PJRC) that the 10x10 requires a more expensive PCB process....
    Thanks for that insight, it's very interesting!

  7. #207
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    Great stuff!
    This monster may render direct camera capture (via parallel interface) viable even without a FIFO!

  8. #208
    Senior Member+ defragster's Avatar
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    MX RT1064 Status :: Development - { More stock available week commencing 1/28/19 }

    Wondering if the MCU cost/footprint tradeoff for included flash and no external part ... and if it is addressed as onchip memory space not QSPI FLASH? Faster and not directly externally readable? And only add a couple months wait and rework on PCB ...

    NXP has posted 1064 doc [14 Nov 2018]: i.MX RT1064 Crossover
    As Paul suggested:: LFBGA196, plastic, low profile fine-pitch ball grid array; 196 balls; 0.65 mm pitch; 10 mm x 10 mm x 1.3 mm body
    The i.MX RT1064 processor has 4 MB on chip Flash and
    1 MB on-chip RAM. 512 KB SRAM can be flexibly
    configured as TCM or general-purpose on-chip RAM,
    while the other 512 KB SRAM is general-purpose on-chip RAM.
    i.MX RT1064 Crossover Processor with ARM® Cortex®-M7 core

    Overview

    The i.MX RT1064 builds on the popular i.MX RT series and is the first i.MX RT family to include On-Chip flash. The i.MX RT1064 provides 4MB On-Chip flash, 1MB the On-Chip SRAM while keeping pin-to-pin compatibility with i.MX RT1050 and RT1060. The i.MX RT1064 runs on the Arm Cortex-M7 core at 600 MHz.

  9. #209
    Senior Member PaulStoffregen's Avatar
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    We're not going to use the 1064 chip. It's not a matter of cost or size, but schedule. We can get 1052 or 1062 in ~14 weeks, but 1064 is an unknown farther point into 2019. I had really hoped to fully release before the end of this year, so we're already months behind schedule. I don't want to delay any more!

    Robin and I have been talking this week about which chip to use. We're going to make the final decision by Tuesday. I had hoped to be able to keep the Teensy 4.0 retail price about the same as Teensy 3.2, but even if we go with the 1052 that's looking unlikely. Going with the 1062 will add about $1.00 to $1.50 (USD). The difference between ~$22-$24 to ~$23-$25 final price seems worthwhile to have so much more RAM, plus the extra little things like faster GPIO & CAN FD. Of course the final pricing will depend on some factors we just don't know yet, but I can tell you we're definitely looking to keep it under $25.

    We're going to start the beta test using the 1052, I hope in mid-December. We bought a couple hundred of those chips earlier this year and they're already over at the contract manufacturer. The first beta test boards will have the pinout of msg #181. Assuming we finalize on 1062 (looking very likely) we'll probably alter the pinout and a 2nd round of beta boards, and maybe a 3rd round much later might have 1062 chips.

    Later in 2019, I hope to make a new "LC" board using the RT1015 or something similar, targeting "under $20" final price. While I can't talk about any details I might know (under NDA) about future chips NXP hasn't announced yet, my hope is to add a high-end board in 2020 using a higher end part.

    We're going to continue making the Teensy 3.x board for quite a long time. They have better analog features and 2 of them are 5V tolerant, which isn't possible with any of the newer parts. The sun will probably set on Teensy 2.0 & Teensy++ 2.0 around 2021.

  10. #210
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    We're not going to use the 1064 chip. ...
    Good answer. Expected that given how long it has taken for 1050/1060 revisions and stock to show ... and still 14 weeks for them in quantity.

    Sounds like it will still beat the price of the Arduino UNO - and a bit more power and functionality

  11. #211
    Senior Member+ Frank B's Avatar
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    Oh..please...more RAM... When I read this, the child in me wants it so bad...
    No, with larger displays for example, or advanced newer applications, or ported pc-libraries.... this *really* makes sense.

  12. #212
    Senior Member+ Frank B's Avatar
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    Did I mention, the simple MP3 decoder need >30KB RAM ? Flac with default blocksize a multiple of that.. not to speak about ENcoding..
    The VGA output wants RAM, and "fullscreen" DMA the ili9314... and..what about better caching for SD? OK I stop now. Time for bed.

  13. #213
    Senior Member+ defragster's Avatar
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    Indeed Frank the RAM would allow the T_4 to make best use of the 600 MHz and "~$23-$25 final price seems worthwhile to have so much more RAM". If the cost ends up near the T_3.5 and it can be all it can be - RAM for code and processing to minimize the Flash wait and overhead. Even half the RAM will come with a wait state and need attention based on usage - but at least it will be there for DMA use or secondary storage buffer.

    Hopefully it looks good to "finalize on 1062 (looking very likely)" as that added cost could allow it to best make use of the increased core speed.
    Last edited by defragster; 11-19-2018 at 07:26 AM.

  14. #214
    So no substitute worth teensy 3.6 before 2020?

  15. #215
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Armadafg View Post
    So no substitute worth teensy 3.6 before 2020?
    Well no, probably not.

    In many ways this could be seen as a replacement or upgrade. This new mid-range ~$24 product has nearly all the features of today's high-end $29 product, plus ~4X faster performance, much more memory, and some pretty awesome new peripherals.

    But in some other sense none of the new products directly replace or substitute for the old... unless NXP manages to give us extremely unlikely silicon next year. Implementing 5V tolerance and higher quality analog is very unlikely due to the physical realities of faster process silicon nodes. NXP's Kinetis chips on Teensy 3.x use a 90 nm process. These new iMXRT chips are somewhere between 28 to 40 nm (haven't gotten a clear answer - this may be something they're just not willing to say anymore). The silicon is physically different and just can't do some of the analog stuff the old parts could - so not a direct substitute.

    2020 probably sounds like a long way in the future, since we're only at the end of 2018 right now. But again, it's important to keep things in perspective. Right now, they've not even publicly announced any parts beyond the RT1064. Usually info first appears on their website and only limited specs in the 2-page "fact sheet" PDF. Typically months later they actually publish the reference manual and some time later early samples become available. Usually it's still more months until the parts actually become buyable in volume. Then there's the lead time to actually get them, which is currently ~14 weeks. But that's all for these current parts which are basically the same as the RT1052.

    Consider how long the RT1052 took. I was told of the chip (under NDA) in 2016. They published the first datasheet & manual (under NDA) in June 2017, and put the first "fact sheet" on their website around that time. Later in the the summer of 2017, the first eval boards shipped (also under NDA) and became publicly available near the end of 2017. But that was the early version of the chip which had severe errata. It was only months ago that the version with full 3.3V power supply compatibility and atomic bit set/clear GPIO became available.

    Hopefully NXP will have a smoother release of whatever next-gen chip comes, well, next. That is, assuming they are going to make add more chips in their iMXRT product line. Anything I might know of their future plans would be under NDA until they actually publish info on their website. But if you carefully compare their many products, it's pretty clear to see the RT1052 is pretty much ARM's Cortex M7 with a mix of stuff from iMX 6 and the newer Kinetis parts, plus some stuff maybe custom (FlexRAM, DC-DC switcher, etc). It doesn't take much imagination to look at their current iMX 7 & 8 product lines to see the pretty incredible IP they've already developed and shipped on high end application processors and hope we might get some of that amazing stuff in future iMXRT. There's also some change they'll surprise everyone with totally new stuff, like when the first Kinetis chips with FlexIO came out a few years back (right around the time Teensy 3.6 was releasing - about 1 year after the K66 chip came out).

    The other reality to consider is PJRC is a small shop with limited resources. I do not believe we've ever managed to release 2 new Teensy models in the same year. So if 4.0 (likely RT1062) and LC2 (maybe RT1015) both make it to market in 2019, that'll be a first for us. Also notice NXP's website says RT1015's status is still "pre-production" and you can't yet download a reference manual or datasheet. It's very unlikely that chip will actually be available in volume until mid-2019 or later.

    Consider the time it's taken Arduino to release new products using a substantially different chip. I believe Leonardo (USB AVR), Due (SAMX) and Zero (SAMD) each took well over a year to come to market (and at least with USB AVR they had Teensy 2.0 available for 3 years for inspiraton....). Even though they're much bigger with more developers, this sort of work to support a new architecture simply takes time. But something we're doing differently than Arduino, which can make this seem much longer, is giving early access and input on the design via the forum. We try to balance this early access with a few politely requested restrictions (mainly not showing photos during beta testing). Often I've wondered if this has been unwise. Certainly one of the downsides to such early access is it really shows the full span of the very long development cycle. Please do try to keep all this in perspective...
    Last edited by PaulStoffregen; 11-19-2018 at 11:21 AM.

  16. #216
    Senior Member+ KurtE's Avatar
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    Hi Paul,

    Sounds like a lot of things to keep you busy

    It must be difficult to try to figure out what path you wish to take PJRC and pick and choose where to apply your resources. Cann't wait to try out the new shiny hardware

    Also probably hard to figure out which features you wish to support. At times I sure wish some new Teensy board would directly support wireless, preferably WiFi and maybe BT.

    One of the things I have trying to play with lately is ROS2 using stuff from Robotis... With this they are also working on being able to make ROS nodes using microcontrollers (ROS2Arduino), and it will be great to make sure there is support for the Teensy boards. Will be able to make sure they work using USB and Serial, but would be really great if it could do it wireless...

    But again I totally understand you only have so many hours in the day...

  17. #217
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    How does the planned pinout for the Teensy 4 compare to the Teensy 3.2, meaning how much compatibility is there between existing boards for the Teensy 3.x family and the new hardware.

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    Quote Originally Posted by daywalker03 View Post
    How does the planned pinout for the Teensy 4 compare to the Teensy 3.2, meaning how much compatibility is there between existing boards for the Teensy 3.x family and the new hardware.
    Have a look on post 184 of this thread and compare to T3.2.
    this is as close one could guess with the information available.

    It seems that for the beta testing the 24 outer pins a fixed, but where all other pads and pins are is not disclosed yet.
    For this to know we have to wait for the first boards shipped. The beta test boards may not even have the final form factor.

    For the final release, which has an other chip than the beta tests, more pin/pad changes are likely (as announced by Paul)

    So, I wait for final layout before changing my boards for the T4

  19. #219
    Senior Member PaulStoffregen's Avatar
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    I can tell you the first round of betas will have the pins in msg #181, including pins 24-33 brought to pads on the bottom side.

    The pinout definitely will change, at least so we have access to the CAN FD pins on the RT1062 chip. The changes are expected to be fairly minor, between 2 to 5 pins altered. If you have any concerned or input about which pins, *NOW* is the time to read the many messages in this thread and start pouring over the info in NXP's RT1050 & RT1060 reference manuals.

    So to directly answer your question about compatibility, the answer can be found in comparing the info from msg #181, and perhaps some reading of NXP's ref manual to understand the pins, against the existing Teensy 3.2 pin info. Yes, this means quite a bit of effort needed on your part. That's the reality of this very early pre-beta stage. As we get farther into the beta, more info will appear on the forum, mostly intended for the folks actually working with the beta boards. Like with prior betas, which you can find on this forum, things will start a little rough around the edges and will gradually improve as we many progress. The plan it to keep all the stuff on this forum, which probably will be inconvenient (as it has been before) and we'll ask everyone with hardware not to take photos, at least until it's officially announced on the website and/or kickstarter. The idea, as before, is to give you early access, but it's done in this forum with only text and maybe simple line diagrams. If you want to have meaningful input, you can, but it takes some work. Likewise, if you want some early info, you can have it here. For easier documentation like the pinout cards, especially with high-res photos, you'll have to wait until closer to release.

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    After reading through the entire thread, I really don't see anything I would specifically change about what you're planning.

  21. #221
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    I can tell you the first round of betas will have the pins in msg #181, including pins 24-33 brought to pads on the bottom side.
    ...
    Seems the Beta boards be in the final 1.4"x0.7" formfactor? Not a Proto size like first K66 boards?

    Would be handy to have a mock up prototype of the 'Teensy 4' pinout card included - that was something that would have helped wiring/testing on the K66. Won't have a schematic yet so it could show the mcu_pin# for clarity of reference?

    Nice you have 1050 chips for beta builds - and even better the 1060 is the real target MCU. The Beta #0 boards will be good for initial test runs - but with pin changes they will be obsolete after Beta #1 changes? Will the later 1050 beta boards have any support after the 1060's come online?

    Sr+ members can post 'unseen' in the moderator thread - is there a way to make a beta+ user group for interim release that would be similar to a thread? Assuming they are trusted(NDA?) members it could allow more fruitful initial progress.

    Is the USB faster than the T_3's 12 Mbps - I wondered but not enough to look yet. You noted running at 400 MHz - does that help with early work or use against scope?

    Does your existing '...\hardware\teensy\avr\cores\teensy3\mk20dx128.c ' "ser_print()" code in " void fault_isr(void) { #if 0 " work to dump out debug on the T_4? Perhaps you've tested to catch faults - that was the base of the debug_t3 library I started to help debug faults.

  22. #222
    Senior Member PaulStoffregen's Avatar
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    Lots of beta questions. I'll answer some now, others later...

    Quote Originally Posted by defragster View Post
    Seems the Beta boards be in the final 1.4"x0.7" formfactor? Not a Proto size like first K66 boards?
    The first betas will be a size somewhere between these. The boards we have now are usable on a breadboard, so nowhere near the 3.0 x 2.5 inch size of the early Teensy 3.6 betas.


    Would be handy to have a mock up prototype of the 'Teensy 4' pinout card included
    Are you saying I should delay sending the first betas until we've had time to make a pinout card?

    I can assure you the documentation will be scant and will leave much to be desired when we ship the first boards. In fact, it'll probably look very much like the table in msg #181. Like last time, the documentation, code and other stuff will improve as we go. Like last time, we're going to ask everyone to refrain from photos or realistic diagrams, until that info is published on Kickstarter and/or the PJRC site. This is less than ideal. It's a trade-off which (hopefully) allows us to share the raw info and invite people to beta test before release - and be open enough to allow anyone interested to follow the forum - yet have an official release.


    Will the later 1050 beta boards have any support after the 1060's come online?
    Support for the 1052-based beta boards will get dropped at or short after the time frame the official 1062 product is released.

    This will be explained (hopefully clearly) when we start the beta. Everyone we offer beta board will have the choice of getting one of these to-be-abandoned 1052 boards early, or waiting until later in the testing cycle to get a 1062 board which will (probably) work long-term with the non-beta release. We might send 2 boards to some highly active people. But everyone who chooses to get a 1052 board early should know support for that chip will get dropped. Save a copy of the last beta installer, or find a project to permanently install the beta board.

    As always, the betas will be offered for free to people we choose. PJRC will pay for shipping. The only cost anyone may have to pay is tariff & fees for international delivery. These betas aren't a normal product where long-term support should be expected. Especially for the early ones with the 1052 chip, they absolutely will have software support abandoned.


    is there a way to make a beta+ user group for interim release that would be similar to a thread? Assuming they are trusted(NDA?) members it could allow more fruitful initial progress.
    We could do this, but I prefer to keep it open. Like before, we're going to ask everyone to avoid photos (until the Kickstarter is live) and keep all code and discussion here on the forum, even if that's inconvenient.


    Is the USB faster than the T_3's 12 Mbps
    Yes, 480 Mbit.


    You noted running at 400 MHz - does that help with early work or use against scope?
    Will talk of this and so many other details when we ship the first 1052 betas.

    Truth is, quite a lot of this stuff is still somehow half-baked right now. Part of the lack of specific detail is things are still changing here...

  23. #223
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Lots of beta questions. I'll answer some now, others later...
    Good answers - only one or two seemed relevant - but I was gone a few days and had some spare typing to catch up on.

    480 Mbit sounds awesome - the poor PC's won't know what hit them - about 40 times over!

    No, by all means ship when ready without delay for paperwork. You have spoiled us with Teensy cards - anyone can use a Teensy, but I wasn't thinking photorealistic - just a copy of the post 181 with minor adds and clear columns in a spreadsheet table would minimize wrong guesses and everyone doing it themselves and perhaps help index into the RM. Of course everyone doing that will learn something in rtfm time …

    "somehow half-baked" - funny - you don't get to keep a 700 Hp car running long on the street without traction control - and that is after it goes on sale. As noted it is a very involved and adjustable feature ridden MCU to exploit and still be user friendly. You tamed the simpler T_3.6 quite well but some of those beta helpers were critical given the breadth of it. And the K66 didn't have the multiple revs and then evolve the 1052 into the 1062.

  24. #224
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    If, and I'm not saying that I personally would like to have the earlier beta board, I did get one, I would probably have an entirely separate system set aside to program them on knowing that they won't be supported in the official release. That way I could use both without having to switch installed versions of teensyduino all the time.

  25. #225
    Senior Member+ defragster's Avatar
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    As Paul noted many of the questions I asked are premature (but got some feedback) and he's awesome at making his plan work as he can support it when he picks the beta users that can best help for the problems and schedule at hand - and all that info will come ... It worked really well for the products released in my time here as they all shipped with working hardware.

    And it's been noted: the only sure way to not get a beta board … is to ask for one …

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