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Thread: SPI speed on Teensy 3.5 is not correct

  1. #1
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    SPI speed on Teensy 3.5 is not correct

    Hi. Today i take a look on SPI clock signal. Despite i have define 400000 for speed, the clk signal is measured at 312000. It's not really a problem for me but perhaps this can impact other features in Teensy..

  2. #2
    Senior Member+ KurtE's Avatar
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    Actually I believe it is working correctly.

    That is the Speed value you pass in, is a value that says SPI shall not exceed this speed.

    You did not specify much here, but if I assume a default build, the T3.5 was built at 120mhz? Which implies that the bus (F_BUS) was defined to be 60mhz.

    The SPI clock is setup by using clock dividers. The two nearest values for clock dividers are:
    128 so 60000000/128 = 468750 which is too big
    and 192 60000000/192 = 312500 which is what you are seeing.

  3. #3
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    Oops, I have made mistakes. It's a Teensy 3.6 and I compile it at 180Mhz. For me, like I said before, it's not a problem and all works fine.
    But it's better to know how it's work and why frequency is different from what's expected.

  4. #4
    Senior Member+ KurtE's Avatar
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    I am glad it is working. I just thought I would mention how it works and options...

    Same difference the T3.6 at 180mhz the F_BUS by default is set to 60mhz...

    If instead you run at 192K than F_BUS = 48K
    Then: 48000000/128 = 375000 which is closer to your desired SPI speed

    Run at 216K -> F_BUS= 54K ... 192 again 281250 worse...

    Note: there are some options in kinetish to change what F_BUS value to use for a speed, by editing the file in the sections that look like:
    Code:
    #elif (F_CPU == 180000000)
     #define F_PLL 180000000
     #ifndef F_BUS
     #define F_BUS 60000000
     //#define F_BUS 90000000
     #endif
     #define F_MEM 25714286
    The F_BUS must be even divided into F_CPU, so you see there is a commented out version of 90mhz...
    but 90000000/192 = 468.... Too big, so next is 256 -> 351562.5 which gets you closer...

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