I would like to get a low jitter clock from Teensy 3.6 to drive an external ADC. Immediate need is for a clock of 2MHz, and the Teensy's 16MHz crystal (or a divided version) would work well.
I do NOT want a clock generated by an on-chip PLL or FLL, unless such has a (low) documented amount of jitter.
I've been Reading the 2200 pages of The Fine Manual, and I'm still not sure how to do this.
Time will probably reveal an answer, but I hope someone has done this before.
Goal is to run a ADS1271 at approx. 4K samples per second (exact rate somewhat flexible).
I do NOT want a clock generated by an on-chip PLL or FLL, unless such has a (low) documented amount of jitter.
I've been Reading the 2200 pages of The Fine Manual, and I'm still not sure how to do this.
Time will probably reveal an answer, but I hope someone has done this before.
Goal is to run a ADS1271 at approx. 4K samples per second (exact rate somewhat flexible).