#ifndef I2S_32_QUAD_H
#define I2S_32_QUAD_H
#include "kinetis.h"
#include "core_pins.h"
#include "AudioStream.h"
#include "DMAChannel.h"
#define NCH 4
class I2S_32_QUAD : public AudioStream
{
public:
I2S_32_QUAD(void) : AudioStream(0, NULL) {begin();}
void begin(void);
virtual void update(void);
void digitalShift(int16_t val){I2S_32_QUAD::shift=val;}
protected:
static bool update_responsibility;
static DMAChannel dma;
static void isr32(void);
private:
static int16_t shift;
static audio_block_t *block_incoming[NCH];
void config_i2s(void);
};
DMAMEM static uint32_t i2s_rx_buffer_32[2*NCH*AUDIO_BLOCK_SAMPLES];
audio_block_t *I2S_32_QUAD::block_incoming[NCH] = { NULL, NULL, NULL, NULL};
bool I2S_32_QUAD::update_responsibility = false;
DMAChannel I2S_32_QUAD::dma(false);
int16_t I2S_32_QUAD::shift=8; //8 shifts 24 bit data to LSB
void I2S_32_QUAD::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
config_i2s();
CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
#ifdef __MK20DX256__
CORE_PIN30_CONFIG = PORT_PCR_MUX(4); // pin 30, PTC11,I2S0_RXD1
#endif
#ifdef __MK66FX1M0__
CORE_PIN38_CONFIG = PORT_PCR_MUX(4); // pin 38, PTC11,I2S0_RXD1
#endif
dma.TCD->SADDR = (void *)((uint32_t)&I2S0_RDR0);
dma.TCD->SOFF = 0;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
dma.TCD->NBYTES_MLNO = (2*4);
dma.TCD->SLAST = 0;
dma.TCD->DADDR = i2s_rx_buffer_32;
dma.TCD->DOFF = 4;
dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer_32) / (2*4);
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer_32);
dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer_32) / (2*4);
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
update_responsibility = update_setup();
dma.enable();
I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
dma.attachInterrupt(isr32);
}
void I2S_32_QUAD::isr32(void)
{
uint32_t daddr;
uint32_t *src;
daddr = (uint32_t)(dma.TCD->DADDR);
dma.clearInterrupt();
if (daddr < (uint32_t)&i2s_rx_buffer_32[AUDIO_BLOCK_SAMPLES*NCH])
{ // DMA is receiving to the first half of the buffer
// need to remove data from the second half
src = &i2s_rx_buffer_32[AUDIO_BLOCK_SAMPLES*NCH];
}
else
{ // DMA is receiving to the second half of the buffer
// need to remove data from the first half
src = &i2s_rx_buffer_32[0];
}
if (block_incoming[0] != NULL)
{
for(int ii=0;ii<AUDIO_BLOCK_SAMPLES;ii++)
{
{ block_incoming[0]->data[ii] = (int16_t) (*(src)>>I2S_32_QUAD::shift); src++;}
{ block_incoming[2]->data[ii] = (int16_t) (*(src)>>I2S_32_QUAD::shift); src++;}
{ block_incoming[1]->data[ii] = (int16_t) (*(src)>>I2S_32_QUAD::shift); src++;}
{ block_incoming[3]->data[ii] = (int16_t) (*(src)>>I2S_32_QUAD::shift); src++;}
}
}
if (update_responsibility) update_all();
}
void I2S_32_QUAD::update(void)
{
unsigned int ii, jj;
audio_block_t *new_block[NCH];
audio_block_t *out_block[NCH];
// allocate NCH new blocks. If any fails, allocate none
for (ii=0; ii < NCH; ii++) {
new_block[ii] = allocate();
if (new_block[ii] == NULL) {
for (jj=0; jj < ii; jj++) {
release(new_block[jj]);
}
memset(new_block, 0, sizeof(new_block));
break;
}
}
}
// MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
//
#if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
// PLL is at 96 MHz in these modes
#define MCLK_MULT 2
#define MCLK_DIV 17
#elif F_CPU == 72000000
#define MCLK_MULT 8
#define MCLK_DIV 51
#elif F_CPU == 120000000
#define MCLK_MULT 8
#define MCLK_DIV 85
#elif F_CPU == 144000000
#define MCLK_MULT 4
#define MCLK_DIV 51
#elif F_CPU == 168000000
#define MCLK_MULT 8
#define MCLK_DIV 119
#elif F_CPU == 180000000
#define MCLK_MULT 16
#define MCLK_DIV 255
#define MCLK_SRC 0
#elif F_CPU == 192000000
#define MCLK_MULT 1
#define MCLK_DIV 17
#elif F_CPU == 216000000
#define MCLK_MULT 8
#define MCLK_DIV 153
#define MCLK_SRC 0
#elif F_CPU == 240000000
#define MCLK_MULT 4
#define MCLK_DIV 85
#elif F_CPU == 16000000
#define MCLK_MULT 12
#define MCLK_DIV 17
#else
#error "This CPU Clock Speed is not supported by the Audio library";
#endif
#ifndef MCLK_SRC
#if F_CPU >= 20000000
#define MCLK_SRC 3 // the PLL
#else
#define MCLK_SRC 0 // system clock
#endif
#endif
void I2S_32_QUAD::config_i2s(void)
{
SIM_SCGC6 |= SIM_SCGC6_I2S;
SIM_SCGC7 |= SIM_SCGC7_DMA;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
// if either transmitter or receiver is enabled, do nothing
if (I2S0_TCSR & I2S_TCSR_TE) return;
if (I2S0_RCSR & I2S_RCSR_RE) return;
// enable MCLK output
I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
while (I2S0_MCR & I2S_MCR_DUF) ;
I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
// configure transmitter
I2S0_TMR = 0;
I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
| I2S_TCR2_BCD | I2S_TCR2_DIV(1);
I2S0_TCR3 = I2S_TCR3_TCE_2CH; // dual tx channel
I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
// configure receiver (sync'd to transmitter clocks)
I2S0_RMR = 0;
I2S0_RCR1 = I2S_RCR1_RFW(1);
I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
| I2S_RCR2_BCD | I2S_RCR2_DIV(1);
I2S0_RCR3 = I2S_RCR3_RCE_2CH;
I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
// configure pin mux for 3 clock signals
CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
}
#endif