Slowing down the PDB

Status
Not open for further replies.

imagiro1

Member
I'm trying to slow down the PDB to something a lot slower - 8kHz.

I've found (I think) where the PDB is set for 44.1kHz in input_adc.cpp and output_dac.cpp.
Code:
// set the programmable delay block to trigger the ADC at 44.1 kHz
#if defined(KINETISK)
	if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
	  || (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
	  || PDB0_MOD != PDB_PERIOD
	  || PDB0_IDLY != 1
	  || PDB0_CH0C1 != 0x0101) {
		SIM_SCGC6 |= SIM_SCGC6_PDB;
		PDB0_IDLY = 1;
		PDB0_MOD = PDB_PERIOD;
		PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
		PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
		PDB0_CH0C1 = 0x0101;
	}
#endif

PDB_CONFIG in utility\pdb.h.
Code:
#define PDB_CONFIG (PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | PDB_SC_CONT | PDB_SC_PDBIE | PDB_SC_DMAEN)

I don't see where PDB_PERIOD is set for 180Mhz in utility\pdb.h. Does it use the default value in PDBx_MOD?

Also, what is the formula for changing the PDB? From the PDBx_SC register.
(1/180MHz/PRESCALRER/MULTI) * PDBx_MOD?

Will changing these settings have any other adverse side-effects when using the audio library?

Lastly, when should these registers be changed? In my mind, this is the last thing in the setup function before moving to the loop.
 
PDB is clocked by F_BUS, freq = F_BUS/PRESCALE/MULT/PDB_MOD
For T3.6@180mhz, F_BUS is 60 mhz, in hardware/teensy/avr/libraries/Audio/utility/pdb.h you'll see to get 44.1 KHz, PDB_PERIOD is conditionally calculated based on F_BUS value (PRESCALE and MULT are 1, value in register is 0)

F_BUS @60mhz, PDB0_MOD = (7500 - 1) will clock PDB at 8 khz

https://forum.pjrc.com/threads/24492-Using-the-PDB-on-Teensy-3
 
Status
Not open for further replies.
Back
Top