Thank you KurtE, I did not know this thing:
"" to use objdump to disassemble code and look to see the actual startup ... ""
Dear Poul, the most correct question would have been: Excuse me, what job do you do? Or what is your profession?
But I could also answer "The boy at the gas station (45 yesrs old boy)".
Like those I know who spend 1000 euros to build Drones alone and program the PID ...... return home.
Instead I am even simpler.
IAR offers the free version limited to 32K, but I can use as much as I want , do not expire .
I also had the opportunity to understand for example that GPIOC_PTOR in the simulator you see it change status only once and then never again. But that register in particular can only be read. Strange because the SIMULATOR also offers the possibility to change defaults. And confusing since you can't see ....so you can't see ! No even one time .......
But being ignorant, I get angry when I do not understand things , especially because I started from a simple function to enter into the vector table and now I find myself trapped because I can not make it run at the frequency that I want.
When I understand these rules, I go back to using TeensyDuino Software which is wonderful.
IAR- Keil - "Arduino" all have different systems to create a file of startup.s, different languages procedure, have differences between them.
I read a lot of that book you suggest , but I is not very useful for this moment problem , because those parts are not treated. The registers are described in detail, with the general operations, but then there is no mention of how to start Clock , not even in the example of the board hi use for his examples, nothing of the startup.s.
And Paul , that guy suggest to install IAR or Keil or GNU .
This are the reasons for all my questions.
Sorry, but if you want to do something, do you try it only once? Take a step back? Or do you try again and try again?
For example, looking, I found this file useful, that tomorrow I'll try to understand the way.
Code:
// If the internal load capacitors are being used, they should be selected
// before enabling the oscillator. Application specific. 16 pF and 8 pF selected
// in this example
OSC_CR = OSC_CR_SC16P_MASK | OSC_CR_SC8P_MASK;
// Enabling the oscillator for 8 MHz crystal
// RANGE=1, should be set to match the frequency of the crystal being used
// HGO=1, high gain is selected, provides better noise immunity but does draw
// higher current
// EREFS=1, enable the external oscillator
// LP=0, low power mode not selected (not actually part of osc setup)
// IRCS=0, slow internal ref clock selected (not actually part of osc setup)
MCG_C2 = MCG_C2_RANGE(1) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
// Select ext oscillator, reference divider and clear IREFS to start ext osc
// CLKS=2, select the external clock source
// FRDIV=3, set the FLL ref divider to keep the ref clock in range
// (even if FLL is not being used) 8 MHz / 256 = 31.25 kHz
// IREFS=0, select the external clock
// IRCLKEN=0, disable IRCLK (can enable it if desired)
// IREFSTEN=0, disable IRC in stop mode (can keep it enabled in stop if desired)
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
// wait for oscillator to initialize
while (!(MCG_S & MCG_S_OSCINIT_MASK)){}
// wait for Reference clock to switch to external reference
while (MCG_S & MCG_S_IREFST_MASK){}
// Wait for MCGOUT to switch over to the external reference clock
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
// Now configure the PLL and move to PBE mode
// set the PRDIV field to generate a 4 MHz reference clock (8 MHz /2)
MCG_C5 = MCG_C5_PRDIV(1); // PRDIV=1 selects a divide by 2
// set the VDIV field to 0, which is x24, giving 4 x 24 = 96 MHz
// the PLLS bit is set to enable the PLL
// the clock monitor is enabled, CME=1 to cause a reset if crystal fails
// LOLIE can be optionally set to enable the loss of lock interrupt
MCG_C6 = MCG_C6_CME_MASK | MCG_C6_PLLS_MASK;
Clocking
Kinetis Quick Reference User Guide, Rev. 3, 05/2014
44 Freescale Semiconductor, Inc.
// wait until the source of the PLLS clock has switched to the PLL
while (!(MCG_S & MCG_S_PLLST_MASK)){}
// wait until the PLL has achieved lock
while (!(MCG_S & MCG_S_LOCK_MASK)){}
// set up the SIM clock dividers BEFORE switching to the PLL to ensure the
// system clock speeds are in spec.
// core = PLL (96 MHz), bus = PLL/2 (48 MHz), flexbus = PLL/2 (48 MHz), flash = PLL/4 (24
MHz)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1)
| SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(3);
// Transition into PEE by setting CLKS to 0
// previous MCG_C1 settings remain the same, just need to set CLKS to 0
MCG_C1 &= ~MCG_C1_CLKS_MASK;
// Wait for MCGOUT to switch over to the PLL
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){}
// The USB clock divider in the System Clock Divider Register 2 (SIM_CLKDIV2)
// should be configured to generate the 48 MHz USB clock before configuring
// the USB module.
SIM_CLKDIV2 |= SIM_CLKDIV2_USBDIV(1); // sets USB divider to /2 assuming reset
// state of the SIM_CLKDIV2 register
****************************************************************
If then this my asking disturbs.
I apologize
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Originally Posted by M.Melani
